Initialization file for block RAM in Xilinx. Coe established

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1. Generate a positive cosine wave floating point value in MATLAB and quantify it as a 16bit fixed-point waveform value:

Another way:

The initialization of Xilinx ROM is a cumbersome thing to import into the Coe file.

Alteral is a MIF and hex file that has specialized software that can be generated.

The format of the Coe file is as follows:

memory_initialization_radix=10;

Memory_initialization_vector=

512,515,518,522,525,528,531,535,538,54

。。。。。。。。 12,23;

Note: The previous 2 lines do not move, the number behind the radix represents the binary, here take 10 binary. It ends with a semicolon.

In MATLAB, the key steps are as follows, we take a period of 1000 samples, the number of bits 10 bits of the sine table as an example.

n=0:999; Y=round (sin (2*pi*0.001*n) *512) +512;//is followed by 512 to prevent negative numbers

Y=mod (y,1024);//Because it is 10 bits, so, no 1024, 1024 take the remainder, convert 1024 to 0

Dlmwrite (' b.txt ', y); the//dlmwrite function allows the resulting data to be separated by commas.

Get the B.txt file, open it with Notepad, add it on top

memory_initialization_radix=10;

Memory_initialization_vector=

At the same time the end of data is terminated with semicolons

Last Save As, select the suffix. Coe, import the file into ROM, click Show, or the button that displays the initial data (different Ise is not the same), indicating that the data is imported correctly.

For ROM modules, the main result is the corresponding. Coe file.

%. Coe file that generates ROM

Clc

Clear All

Close all

x = Linspace (0, PI/2, 1024); % 1024 points at intervals between intervals [0,2PI]

Y_cos = cos (x);

Y_sin = sin (x);

Y_cos = Y_cos * 2^16;

Y_sin = Y_sin * 2^16;

FID = fopen (' d:/cos_coe.txt ', ' wt '); fprintf (FID, '. 0f \ n ', Y_cos);

Fclose (FID);

FID = fopen (' d:/sin_coe.txt ', ' wt ');

fprintf (FID, '. 0f \ n ', y_sin);

Fclose (FID);

2. Generate the. Coe file. under the D packing directory, change the suffix of cos_coe.txt and sin_coe.txt to. Coe. Open the file, the space between each line with the text substitution function for "," (this can be achieved through the powerful UltraEdit!) ), and add a semicolon ";" on the last line. Finally, add the following two lines at the beginning of the file:

memory_initialization_radix=10;

Memory_initialization_vector=

Then, save the file to exit.

3. Load the Coe file into the ROM generated by the Blockrom . Create a new Blockrom IP Core with the location "Memories & Storage Elements---->rams & ROMs----->block Memory Generator v2.4". On page 1th, select "Single Port Rom", on page 2nd, select a bit width of 16, a depth of 1024, download the Coe file on page 3rd, and then double-click Finish to complete the generation of the IP core. If the Coe file is not generated, the previous box in browse is displayed with a red file name, and the Coe file error type mainly has incorrect data cardinality and the length of the data is not two.

Modelsim under ROM emulation.

Using the Xilinx chip to do FPGA development time using ROM, certainly to the ROM to do simulation, after a day of effort, finally can do simulation, now the process is written out for your reference.

1. First you need to compile the Xinlinx library file, there are three library Xinlixcorelib,unisims,simprims, the compilation process in the previous post.

2.Modelsim does not support MIF file only support hex file, here need to convert the file, download dll file Convert_hex2ver.dll:

http://www.eccsdk.com/bbs/read.php?tid=1562&fpage=2

3. Modify the configuration file Modelsim.ini file in the Modelsim installation directory to

List of dynamically loaded objects for Verilog PLI applications

; Veriuser = VERIUSER.SL

Revision changed to

List of dynamically loaded objects for Verilog PLI applications

Veriuser = C:/modeltech_6.1e/win32/convert_hex2ver.dll

Where C:/modeltech_6.1e/win32/convert_hex2ver.dll is the location where the DLL file is saved

4. Copy the ROM.V and rom.mif files to the same directory, the first time you need to load the Xilinx simulation library in the simulation, and then follow the general simulation process.

Initialization file for block RAM in Xilinx. Coe established