Intel manual-Chapter7-Task Management, intelmanagement driver

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Intel manual-Chapter7-Task Management, intelmanagement driver
This section describes the task management function of the IA-32 architecture, which is effective only when the processor runs in the protection mode, this section focuses on the 32-bit task and the 32-bit TSS structure, for more information about 16-bit tasks and the 16-bit TSS structure, see section 7.6. For details about Task Management in 64-Bit mode, see section 7.7 task management overview a task is a unit of work that can be scheduled, executed, and paused by a processor. It can execute a program, task, process, operating system service program, and interrupt routine, exception routines. The kernel utility 32-bit architecture provides a mechanism to save the task status, schedule the task to be executed, and switch one task to another, when the operating system is in the protection mode, all processor Execution occurs in the task. Even a simple operating system, at least one task must be defined, complex operating systems can use the task management function of the processor to support multi-task program 7.1.1 The Task Structure task consists of two parts: the task execution space and the task status segment (TSS ), the task execution space consists of a code segment, a stack segment, and one or more data segments. If an operating system or executable program uses the processor's permission-level protection mechanism, the task execution space also provides a separate stack that specifies the segments that constitute the task execution space for each permission-level TSS and provides storage space for task status information. In a multitasking system, TSS also provides a link task mechanism for tasks to be defined by its TSS segment Selection Sub-defined. When the processor loads a task and executes it, the segment selects the sub-, base address, the limit and TSS segment descriptor attributes are loaded into TR (For details, refer to 2.4.4). If the task is executed in paging mode, the base address of the page directory used by the task is loaded into the 7.1.2 task status in March 3. The following items define the status of the currently executing Task 1. select the current execution space (cs ds ss es fs gs) of the sub-defined task from the segment register. general Register status 3. status of the eflags register 4. status of the EIP register 5. the status of the audit register. 6. TR register Status 7. LDTR register status 8. IO ing base address and IO ing (exist in TSS) 9. the stack pointer of privilege level 0, 1, and 2 (exists in TSS) 10. before a task is scheduled, all the preceding information except the TR register status is included in the TSS. Similarly, all content of the ldtr register is not stored in TSS. Only the LDT segment Selection Sub-exists 7.1.3. to execute a task software or processor, you can use the following method to schedule a task to execute 1. explicitly CALL a task using the CALL command 2. explicitly jump to the task using the JMP command 3. explicitly call an interrupt processing program task (through the processor) 4. explicitly call an exception handler Task 5. A return (an IRET command). When the NT mark in the EFLAGS register is set to 1, all the methods used to schedule a task identify that the task is scheduled, in addition, the segment Selection Sub-points to the TSS of a task door or task. When a task is scheduled using the CALL command or JMP command, you can select a TSS sub-task in the command or save the TSS sub-task. When a task is scheduled to handle an interruption or exception, the IDT item must contain a selection sub-task for saving the interrupted or exception handling program TSS. When the task is to be scheduled for execution, the task switchover occurs between the currently executed task and the scheduled task. During the task switchover, the execution environment of the currently executed task (the status or context of the task) the task is saved in its TSS and paused. The execution environment of the scheduled task is loaded into the processor. The newly loaded EIP register points to the command for starting the task, if the task is not running after the previous system initialization, EIP will execute the First Command of the task code. Otherwise, when the task is active last time, it will point to the last command after the last task is executed. If the currently executed calling task is called by a scheduled task, then, the segment selection child of the calling task is saved in the tss of the called stack and provided to the calling task as link back. For all 32-bit processors, the task is not recursive, A task cannot be called or the JMP is interrupted by itself, and can be switched and processed by Handler tasks. The processor executes a task Switch to handle interruptions or exceptions, in addition, the system automatically switches from an interrupted program task or an abnormal program task to the interrupted program. This mechanism can also handle the interruption that occurs during the interrupted task as part of the task switch, the processor can also switch to another LDT, In the LDT-BASED segment, allowing each task to have a logical address to the physical address ing, when the task is switched, the page Directory base address register C3, each task is allowed to have its own page table. This protection mechanism helps isolate tasks and prevents interference between tasks. If the protection mechanism is not used, the processor does not provide protection between tasks. Even if the operating system uses multiple types of permission-level protection, a task runs on R3 and uses the same LDT and page table as other R3 tasks to access the code, the stack of wrong data and other tasks uses the task management function to process multi-task applications is optional, multi-task can be processed in the software, each software-defined task is executed in the context of a single IA-32 architecture task

7.2 Task Management Data Structure

The processor defines five task-related data structures

1. Task status segment (TSS)

2. Task gate Descriptor

3. TSS Descriptor

4. Task register

5. NT Flag in the EFLAGS register

In the protection mode, at least one task, one TSS or TSS descriptor must be created, and the TSS segment Selection Sub-must be loaded into the TR register.

7.2.1 task Status section-TSS

The processor status information to be restored by the task is stored in the TSS called the system segment. The figure 7-2 explicitly shows the 32-bit CPU. the TSS format of the task is as follows: dynamic and Static Fields

During task switching, when a task is paused, the processor updates dynamic fields. The following are dynamic fields.

1. Common Register fields: EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP

2. segment register field: CS DS ES SS FS GS

3. EFLAGS register

4. EIP register Field

5. link field of the previous task: contains the TSS segment selection child of the previous task (update the task switchover caused by call interrupt exception initialization ), this field (sometimes called the back link field) allows a task to return to the previous task using the IRET command.

When the processor reads static fields, it usually does not change them. These fields are set when the task is created. The following are static fields.

1. LDT disconnected selection subfield: contains the LDT segment selection subfield of the task

2. Control Register field: contains the base address of the page table used by the task, which is also called PDBR.

3. permission level 0 1 2 stack pointer fields: These stack fields contain the logical address composed of the stack segment Selection Sub (SS0 SS1 SS2) and the intra-stack offset (ESP0 ESP1 ESP2, for a specific task, these fields are static. If Stack switching occurs in the task, SS and ESP will change.

4. T-FLAG (debug trap): When this flag is set, when the task is switched to this task, T-flag will cause a debugging exception to the processor

5. i/O bitmap base address field: contains a 16-bit offset from the base address in the TSS to the I/O allow bitmap and interrupt redirect bitmap. If yes, these mappings are stored in a higher address in the TSS. the I/O ing base address points to the base address of the I/O allowed bitmap and the end of the interrupted redirection bitmap.

If pagination is used:

1. during task switching, when the processor reads 104 bytes, TSS exists on two physical pages (that is, only some TSS page boundaries), and the processor may execute incorrect address translation, during task switching, the processor reads and writes 104 bytes of the TSS of each task (using a continuous physical address as the physical address of the first byte of the TSS). If the 104 bytes are not physically consecutive, the processor will access information that does not make money, and will not generate PF exceptions.

2. The physical page of the previous task and the TSS of this task, and each Descriptor Table item should be marked as readable and writable.

3. During task switchover initialization, if pages containing these structures exist in the memory, the task switchover will be executed faster.


7.2.2 TSS Descriptor

Similar to other segments, TSS is defined by segment descriptors. 7-3 of the image explicitly adopts the TSS descriptor format. The TSS descriptor can only be in GDT and cannot be in LDT or IDT.

During CALL and JMP, attempting to use a segment with the TI bit of 1 (representing the current LDT) to select a sub-Access to TSS will cause GP exceptions. During the IRET period, it will cause invalid TSS exceptions (# TS), and attempts to load the TSS segment Selection Sub-to other segment registers will also cause GP exceptions

The Busy-Flag of the type field indicates whether the task is Busy. A Busy task indicates that it is running or paused. If the value of the type field is 1001B, it indicates an inactive task, if the type field is 1011B, it indicates a Busy task. The task will not be recursive. The processor uses Busy-FLag to detect a task that has been interrupted, to ensure that a Busy-Flag is only related to one task, each TSS should have only one TSS descriptor pointing to it


The base address, segment boundary, DPL, G, and P functions are similar to those used in data segment descriptors. In 32-bit TSS, if the G of the TSS descriptor is 0, the limit value must be greater than or equal to 67 h, and the minimum size of TSS is greater than 1 byte. In this way, we try to switch the task where the limit of a TSS descriptor is less than 67h, it will cause invalid TSS exceptions (# TS). If an I/O allows bitmap or the operating system stores additional data, the Limit is more demanding, during task switching, the processor does not check whether the Limit value is greater than 67 h. However, when I/O is accessed to allow bitmap or interrupt the redirected bitmap

Any program access descriptor can use CALL or JMP to schedule tasks (the program CPL value must be smaller than the TSS descriptor's DPL)

In most systems, the DPL value of the TSS descriptor is smaller than 3, so only privileged software can perform task switching. However, in Multitasking Applications, some TSS descriptor DPL may be set to 3, allowing task switching to happen in R3 Program

7.2.3 TSS descriptor in 64 Mode

In 64-Bit mode, task switching is no longer supported, But TSS descriptors still exist. TSS descriptors are extended to 16 bytes. This extension is also applied to LDT and describes the encoding information of system type fields.


7.2.4 task register

The task register stores the entire segment descriptor (32-bit base address (64-bit in IA32-E mode) of the 16-bit segment selector and the TSS of the current task, 16-bit segment boundary and descriptor attribute ), this information is copied from the segment descriptor of the current task GDT and displays the path where the processor uses this information to access the TSS.

The task register has visible and invisible parts (which can be read and can be modified by software) (maintained by the processor, and the software cannot be accessed), and the segment Selection Sub-is in the visible part, pointing to the TSS descriptor in GDT, the processor uses the invisible part of the task register to cache the TSS segment descriptor. caching these values into the Register can make the task execution more efficient, LTR (loaded to the task register) and STR (read Task register) commands load and read visible part of the task register

The LTR command loads a segment to select a child to the task register and points to the TSS descriptor in a GDT. Then it loads information from the TSS descriptor to the invisible part of the task register, LTR is a privileged command that can be executed only when CPL is 0. It is used to push an initial value to the task register during system initialization, then, when the task switchover occurs, the content of the task register is implicitly changed.


The STR command stores the visible part of the task register to the common register or memory. To determine the task currently being executed, the code that executes this command can be used at any privileged level. Generally, it is used only by operating system software.

When the processor is powered on or recharged, the segment selection and base address are set to 0 by default, and the limit is set to FFFFh.

7.2.5 task gate Descriptor

The task gate descriptor provides an indirect, protected task. It can be located in GDT, LDT, or IDT, and the segment of the task gate descriptor selects sub-fields, point to the TSS descriptor in a GDT. The RPL of this segment is not used.

During a task switchover, the DPL of the task gate descriptor controls access to the TSS descriptor. When a program passes through the task gate, it executes CALL or JMP to a task, the CPL and RPL fields of the sub-tasks must point to less than or equal to the DPL of the task gate descriptor. When a task gate is used, DPL of the target TSS descriptor is not used.

The task can be accessed by the task gate Descriptor and TSS descriptor. These structures meet the following requirements:

1. A task requires only one busy-flag: Because the busy-flag of a task is stored in the TSS descriptor, each task should have only one TSS descriptor. However, several job portals may reference the same TSS Descriptor

2. you need to provide selective access to the task: the task gate meets this need because they can exist in ldt and their dpl is different from the DPL of the TSS descriptor, the program does not have sufficient permissions to access the TSS descriptor of a task in GDT, but it may allow access to the task through the Higher DPL task gate of the task gate, and restrict access to special tasks, the task gate provides a larger scope.

3. an independent task is required to handle interruptions or exceptions: The task gate can also exist in the IDT, allowing the interrupt and exceptions to be handled by the task handler, when an interrupt or exception vector points to a task gate, the processor switches to the specified task.

Demonstrate how GDT's job gate, LDT's job gate, and IDT's job gate point to the same job's


7.3 Task Switching

In the following situations, the processor moves to another task for execution.

1. The current program or task executes a CALL or JMP command to a gdt tss descriptor.

2. The current program or task executes a CALL or JMP command to a GDT or current LDT task gate descriptor.

3. An interrupt or exception vector points to the task gate descriptor in an IDT.

4. When the NT flag of the EFLAGS register is set to 1, the current task executes an IRET command.

JMP, CALL, And IRET commands, like interrupt and exception, are redirected to a program mechanism, referencing a TSS descriptor or a job gate (calling or Jmping to a job) or the status of NT flag (when an IRET command is executed) depends on whether a task is switched

When switching to a new task, the processor performs the following operations:

1. Obtain the TSS segment of the new job from the link field of a job or previous job (the job initialized using the IRET command) and select the child as the operand of the JMP or CALL command.

2. check whether the current task is allowed to switch to a new task. The data access privileged rule applies to the JMP and CALL commands, the CPL of the current task and the RPL of the new task segment must be smaller than or equal to the TSS descriptor or the DPL of the referenced task gate. Exception, interruption (except for the interruption caused by the int n command), and the IRET command are allowed to switch tasks regardless of the destination task gate or the DPL of the TSS descriptor. For the interruption caused by the INT n command, DPL is checked

3. Check whether the TSS descriptor of the new task is marked as exists and has a valid limit (the limit must be greater than or equal to 67 h)

4. Check whether the new task is available (call jmp exception or interrupted) or busy (IRET return)

5. Check that the current TSS, new TSS, and all segment descriptors are paged in the system memory.

6. if the task is initialized by a JMP or IRET command, the processor clears the busy flag of the TSS descriptor of the current task. If a call command is used for initialization, the task is interrupted, or an exception occurs, busy flag is set to 1

7. if the task switchover is initiated by an IRET command, the processor clears the NT flag temporarily saved in the EFLAGS register image. If a jmp call is interrupted or an exception occurs during initialization, the NT flag stored in the EFLAGS image remains unchanged.

8. save the status of the current task to the TSS of the current task. The processor finds the current TSS base address in the TR register and copies the status of the following registers to the current TSS: All General registers, segment Selection Sub-in the segment register, the image temporarily saved in the EFLAGS register, and the EIP of the instruction pointer register

9. If the task is switched with a CALL command, an exception, or an interrupt initialization, the processor sets the NT flag in the EFLAGS register loaded to the new task to 1. If the initialization is an IRET command or a JMP command, the NT flag reflects the status of the NT in the EFLAGS loaded from the new task.

10. If the task is initialized with a CALL command, JMP command, exception or interrupt, the processor sets the busy flag of the new task TSS descriptor to 1. If it is initialized by the IRET command, busy flag will not be set

11. Load the task register segment Selection Sub-and new task TSS Descriptor

12. Status of TSS loaded by the processor: LDTR register, PDBR (audit register), EFLAGS register, EIP register, common register, and segment selection sub-register. An error occurs during loading of these statuses, which may cause damage to the architecture status (if the paging mode is not enabled, the PDBR value is read from the TSS of the new task, but it is not loaded into the S3)

13. If the descriptor associated with the segment Selection Sub-item is loaded, any errors that occur in the context of the new task during the descriptor loading process may damage the architecture status.

14. Start executing the new task (the first command that appears in the new task is not executed for the exception routine)


If all the checks and saves have been successfully executed, the processor submits the task switchover. If an unrecoverable error occurs during step 1-11, the processor does not complete the task switchover, make sure that the processor returns to its status before executing the command for switching the initialized task.

If an unrecoverable error occurs in step 12, the architecture status may be damaged, but the error before the execution environment will be processed.

If an unrecoverable error occurs in Step 13, the processor completes Task Switching and generates an appropriate exception before executing the command for the new task

If an exception occurs in Step 14, the exception handler must complete its own task switching before the processor can start to execute a new task.


The status of the currently executed task is always saved. When the task switchover succeeds, if the task is restored, the commands that start to be executed are directed by the value saved in the EIP, and the register is restored to the value when the task is paused.

When a task is switched, the privilege level of the new task does not inherit the privilege level of the paused task. The new task starts to run at the privilege level specified by the CPL field of the CS register of the TSS, because tasks are isolated from TSS, because privileged-Level Rules control access to a TSS, the software does not need to perform the displayed privileged-level check on task switching.

Displays the exception conditions checked by the processor during Task Switching. If an error is found and the error code is referenced, It also displays the exceptions generated by each check (the Check order in the table, the sequence is used in the P6 family processor. The extra sequence is in special mode, which may be different in 32-bit Other Processors ),If they try to reload the segment with exceptions,The exception routine specifies that processing these exceptions may be recursively called. The exception should be fixed before the sub-selection is reloaded.

Each time a task is switched, the TS flag of the CR0 register is set to 1. When other processors generate a floating point exception, the system software uses TS flag to coordinate floating point unit operations. TS flag identifies the context of the floating point unit and the current task may be different.

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