Intel64 and IA-32 Architecture Optimization Guide Chapter 1-7th data hardware prefetch, 7.2 prefetch and cache-related instructions

7.2 hardware prefetch of data

Pentium M, Intel Core solo, Intel Core Duo processors, and Intel Core micro-architecture-based intel netburst processors provide hardware data prefetch mechanisms, this mechanism monitors the application data access mode and automatically fetches data. This action is automatic and does not require programmer intervention.

For intel netburst-based processors, the features of the hardware data prefetch include:

1. It needs two successive cache failures in the last cache to trigger this mechanism; the two cache failures must meet the condition that the cache failure span is shorter than the trigger distance of the hardware prefetch mechanism (see Table 2-23 ).

2. Try to keep 256 bytes forward from the current data access location.

3. Only one stream (loading or storage) is followed on each 4 K page ).

4. You can prefetch up to eight independent streams at the same time from eight different 4 K byte regions.

5. Do not prefetch across 4 K byte boundaries. This is independent from the paging mode.

6. prefetch data to Level 2/Level 3 cache.

7. Do not prefetch the UC or WC storage type.

8. Focus on loading and storage streams. Publishing a read data for a stored stream is a proprietary read (RFO) Transaction and publishing read data for the loaded stream.

In addition to the 2nd and 4th items mentioned above, most of the other features are also applied to Pentium M, Intel Core solo, and Intel Core Duo processors. The hardware prefetch implemented in the Pentium M processor retrieves data to a second-level cache. It can track 12 independent streams forward and 4 independent streams backward. The hardware prefetch of the Intel Core solo processor can track 16 forward streams and 4 backward streams. On the Intel Core Duo processor, the hardware prefetch retrieves data independently from each core.

The hardware prefetch Mechanism Based on Intel core microprocessor is discussed in section 3.7.3 and section 3.7.4. Despite the differences in hardware implementation technology, the overall benefit of hardware prefetch on software is similar between the Intel Core microarchitecture and the previous architecture.

7.3 prefetch and cache-related commands

Prefetch commands inserted by programmers or compilers are on Pentium 4. Before data is actually needed, access the data of at least two cache rows (the data of one cache row on the Pentium M processor ). This hides the latency of data access when you need to process data that has been stored in the cache.

Many algorithms can provide information about the data to be requested in advance. When memory access is in a long, fixed data access mode, the automatic hardware prefetch should be biased towards software prefetch.

Data Reference modes can be divided into the following types:

● Temporary -- data will soon be used again

● Space-data will be used in adjacent locations (for example, in the same cache row)

● Non-temporary-data is accessed once, but will not be reused in the near future (for example, for some multimedia data types, as the vertex cache of a 3D graphics application)

These data features are used in the following discussion.