Internal delay and external delay for non-blocking assignment

Learning Verilog for a while, literally understanding that the difference between blocking and non-blocking is straightforward. The former is serial, mainly used to describe combinatorial logic, and is similar to the assignment in software; the latter is parallel and is mainly used to describe the temporal logic.

However, when mixed with internal delay and external delay, various unexpected situations occur.

As described below, for non-blocking assignments, the results of internal and external delays are very different.

Example 1: Assuming a positive jump along the pclock at 5ns, and current_state before the positive jump, the value is 5, the positive jump appears 3ns after the change to 7, the following two always statements Next_state_h and Next_state_ What will be the value of l?

Always @ (Posedge pclock)    #7 next_state_h <= current_state;always @ (posedge pclock)     next_state_l <= #7 Current_state;

After analysis, next_state_l <= #7 current_state can be decomposed into two words: 1) temp <= next_state_l; 2) #7 next_state_l <= temp; So despite the delay of 7ns, next_state_l gets the value of the Current_state (5) that corresponds to Pclock's transition. The concrete simulation results are as follows

Example 2: Slave_clock of phase delay is generated according to known Master_clock.

' Timescale 1ns/1ps

Module Clock_shift (MASTER_CLK, SLAVE_CLK);
Output Reg MASTER_CLK;
Output Reg SLAVE_CLK;
Parameter TON = 2, TOFF = 3, Tdelay = 5;

Always
Begin
#tON master_clk = 0;
#tOFF MASTER_CLK = 1;
End

Always @ (MASTER_CLK)
SLAVE_CLK <= #tDELAY master_clk;
Endmodule

The simulation waveform diagram is as follows

However, if the #tdelay is prevented from being externally, such as #tDELAY slave_clk <= MASTER_CLK, then the simulation graph will become as follows:



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Internal delay and external delay for non-blocking assignment