Interrupt set/clear-active registers of distributor, gicd_is/cactivern

Set active register, as its name implies, is to set an interrupt to active state, and clear active register is to clear the active state. here we need to explain some concepts of the interrupt state:

Active: If the processor is processing the interrupt processing function at this time, we can say that the interrupt is active at this time;

Pending status: if an interrupt is generated but not processed by the processor, we can say that the interrupt is in pending status;

Inactive status: if an interruption is neither active nor pending, it is called inactive;

Active and pending status: If the processor is executing an interrupt processing function, the interrupt source generates another interrupt, which is called active and pending;

For the set active register, write 1 is valid, write 0 is invalid; read value indicates active, if it is 1, it indicates that the interrupt is active; the offset between this register and distributor is 0x300-0x37c. The calculation method is as follows:

For interrupt IDM, When Div and MoD are the integer division and modulo operations:

The corresponding gicd_isactivern number,N, Is givenN=MDiv 32

The offset of the required gicd_isactivern is (0x300 + (4 *N))
The bit number of the required set-active bit in this register isMMoD 32.

For the clear active register, write 1 is valid, write 0 is invalid; read value indicates active, if it is 1, it indicates that the interrupt is active; the offset range of this Register relative to distributor is 0x0000-0x3fc. The calculation method is as follows:

For interrupt IDM, When Div and MoD are the integer division and modulo operations:

The corresponding gicd_icactivern number,N, Is givenN=MDiv 32

The offset of the required gicd_icactivern is (0x380 + (4 *N))
The bit number of the required clear-active bit in this register isMMoD 32.

Interrupt set/clear-active registers of distributor, gicd_is/cactivern