Interruption of STM32

1, NVIC

Nested vectored Interrupt Controller: can be nested vector interrupt controllers (NVIC)

• NVIC characteristics
  

  
  

  1. 82 unshielded Interrupts # #不包括内核的16个中断
  2. 16 Programmable Priority # #适用于全部中断
  3. Low latency exception and interrupt handling
  4. Power Management Control
  5. Implementation of System control register

The Nvic is tightly coupled to the processor core interface for efficient and fast interrupt response. All interrupts, including kernel exceptions, are managed by NVIC. 2, interrupt vector table in fact interrupt vector table in the **stm32f4xx** startup file can be seen, the details can be seen: [stm32f4xx start file analysis] (http://blog.csdn.net/u013904227/article/ details/51168546) 3, Exti (External interrupt/event Controller) external interrupt/Event Controller main features

1. Independent triggering and masking on each interrupt/event line
2. There is a dedicated status flag bit for each interrupt
3. Generates up to 23 software event/Interrupt requests
4. Detects external signals with a pulse width shorter than the APB2 clock cycle

Interrupt and Event Configuration

• Hardware interrupt Selection

  Configure 23 lines for the interrupt source to refer to the following configuration steps:

  1. Configuring the Shield bit for the 23 interrupt line (EXTI_IMR)
  2. Trigger select bit for line break in configuration (EXTI_RTSR and EXTI_FTSR)
  3. Configuration control NVIC IRQ channel enable and shielding bit to make an interrupt from the 23 line can be correctly answered, NVIC IRQ is mapped to external interrupt controller (EXTI)

• Hardware event Selection

  Configuring 23 lines for the event source can refer to the following configuration steps:

  1. Configuring the Shield bit for the 23 event line (EXTI_EMR)
  2. Configure trigger selection bits for event lines (EXTI_RTSR and EXTI_FTSR)

• Software Interrupt/Event selection

  The 23-wire can be configured as a software interrupt/event line. The following steps can result in a software outage.

  1. Configuring the Shield bit for 23 event/Interrupt line (EXTI_IMR, EXTI_EMR)
  2. Setting the answer bit for the software Interrupt register (exti_swier)

External interrupt/Event mapping

The 140 GPIO pins of the STM32F407ZG are connected to an external wire break, specifically:

The above 16 Exti lines are used, and the remaining 7 Exti lines are connected using the following:

• Exti 16 connection to PVD output (PVD: power-down detection)
• Exti 17 connecting to the RTC Alarm event
• Exti 18 Connect to the USB OTG FS Wakeup Event
• Exti 19 connection to Ethernet Wakeup event
• Exti 20 connection to USB OTG HS (configured in FS) Wakeup event
• Exti 21 Connection to RTC Tamper and TimeStamp event
• Exti 22 connecting to the RTC Wakeup event

The difference between an interrupt and an event

A hardware interrupt/event is generated:

• Input line inputs external signal
• Edge detection Circuitry detects level changes (level change detection can be artificially configured, and rising edge detection is independent from falling edge detection)
• Through one or gate, this or gate connection level detects the output of the circuit with the software Event/interrupt register. So the value of any one line is true, then the output is true, so a soft trigger interrupt or event can be generated
• or gate input signal through two and the door, and the other with the gate and interrupt screen register and the event screen registers connected, control interrupt or event generation. These two are also independent, so you can generate interrupts and events at the same time
• If it is interrupted, the output signal will go through the interrupt suspend request register, if at this time the chip is in a non-interrupted interrupt, you can configure the interrupt suspend register to temporarily suspend an interrupt. Requires software involvement
• If it is an event, the output signal is directly output to a pulse generator, the pulse generator can generate a pulse, and mobilize the corresponding hardware to complete the event response. No software involvement required

Examples of DMA transfers:

• If the configuration is interrupted, you need to enter the interrupt handler after the interrupt has been generated, trigger the DMA operation in the interrupt handler, and then perform the DMA.
• If configured as an event, the DMA operation is triggered directly by the final output pulse of the event and does not require the interrupt processing function to trigger the DMA.

Events can reduce the load on the CPU and improve response speed

4, the core of the most important two modules (Scb:system controller block nvic:nested vectored interrupt Controller) Core Peripherals

SCB

Address	Register Name	Read and Write permissions	Privileged	Reset Value	function Description
0xe000e008	Actlr	RW	Privileged	0x00000000	Auxiliary Control Register
0xe000ed00	CPUID	Ro	Privileged	0x410fc240	ID number of the CPU
0xe000ed04	Icsr	RW	Privileged	0x00000000	Interrupt Control and Status register
0xe000ed08	Vtor	RW	Privileged	0x00000000	Interrupt vector table offset, generally only two values, the 29th bit 1 for the SRAM area, 0 for the code area
0xe000ed0c	Aircr	RW	Privileged	0xfa050000	Application interrupts and resets
0xe000ed10	Scr	RW	Privileged	0x00000000	System control
0xe000ed14	Ccr	RW	Privileged	0x00000200	Configuration and control
0xe000ed18	SHPR1	RW	Privileged	0x00000000	System Interrupt handling function Priority Register 1
0xe000ed1c	SHPR2	RW	Privileged	0x00000000	System Interrupt handling function Priority Register 2
0xe000ed20	SHPR3	RW	Privileged	0x00000000	System Interrupt handling function Priority Register 3
0xe000ed24	Shcrs	RW	Privileged	0x00000000	System interrupt processing function control and state
0xe000ed28	Cfsr	RW	Privileged	0x00000000	Configuring the Exception Status register
0xe000ed28	Mmsrb	RW	Privileged	0x00	Memory Management Exception Status register
0xe000ed29	Bfsrb	RW	Privileged	0x00	Bus Exception Status Register
0xe000ed2a	Ufsrb	RW	Privileged	0x0000	Using the Exception status register
0xe000ed2c	Hfsr	RW	Privileged	0x00000000	Hardware Exception Status Register
0xe000ed34	Mmar	RW	Privileged	Unknown	Memory Management Exception Address register
0xe000ed38	BFAR	RW	Privileged	Unknown	Bus Exception Address Register
0xe000ed3c	Afsr	RW	Privileged	0x00000000	Auxiliary Exception Status Register

NVIC

Address	Register Name	Read and Write permissions	Privileged	Reset Value	function Description
0xe000e100-0xe000e11c	Nvic_iser0-nvic_iser7	RW	Privileged	0x00000000	Interrupt Enable
0xe000e180-0xe000e19c	Nvic_icer0-nvic_icer7	RW	Privileged	0x00000000	Interrupt Prohibition
0xe000e200-0xe000e21c	Nvic_ispr0-nvic_ispr7	RW	Privileged	0x00000000	Interrupt pending
0xe000e280-0xe000e29c	Nvic_icpr0-nvic_icpr7	RW	Privileged	0x00000000	Interrupt Recovery
0xe000e300-0xe000e31c	Nvic_iabr0-nvic_iabr7	RW	Privileged	0x00000000	Interrupt activation
0xe000e400-0xe000e4ef	Nvic_ipr0-nvic_ipr59	RW	Privileged	0x00000000	Interrupt Priority level
0xe000ef00	STIR	WO	Configurable	0x00000000	Software triggered interrupts

5. Priority grouping concept cortex M4 priority groupings as shown

Grouping of kernel priorities:

It is important to note that only 4bits bits (high 4 bits) are used in the STM32F407ZG, which means that the grouping is as follows

tr> Td>2 Td>[5:4] Td>[7:5]

STM32 Group number	prigroup	Binary point	Group Priority bits< /th>	subpriority bits	Group priorities	subpriorities
0	0b111	b.yyyyyyyy	None	[7:4]	1
1	0b110	bx.yyyyyyy	[7]	[6:4]	8
2	0b101	bxx.yyyyyy	[7:6]	4	4
3	0b100	bxxx.yyyyy	[4]	8	2
4	0b011	bxxx x.yyyy	[7:4]	None	+	1

The group numbers in the STM32 are reversed in the kernel manual, which is designed for compatibility, meaning that if the program is ported to a system that supports only 3-bit priority settings, it can run. There are three different design methods are: Use high 4bits, uncorrupted set no reversal, use low 4bits, uncorrupted set number is not reversed, use low 4bits, uncorrupted set number reversal. These three methods are not advisable if they are written in a kernel grouping and then find that there are exactly the same priorities.

• To understand priority groupings, two concepts need to be identified: preemption priority (Group priority), response priority (sub-priority)
  

1. Preemption priority: Nested can be interrupted. That is, when an interrupt occurs, another interrupt with a higher preemption priority than this interrupt level can interrupt an ongoing interrupt until the higher priority interrupt execution is completed before it is returned to continue the interrupted interrupt.
2. Response Priority: No nesting can be interrupted. In other words, when multiple interrupts occur simultaneously, only the corresponding higher priority interrupts can be prioritized, and if a higher priority interrupt occurs during the interrupt, the ongoing interrupt cannot be interrupted.
   The relationship between preemption priority and response priority is somewhat like the difference between a network number and a subnet number in a TCP/IP protocol, and two interrupts are prioritized first and then compared to the response priority.

6. Program Writing

#Define sum_nvic_priotity_bits 4//Total used 4 bits/* Interrupt Priority Group * Group_num: Group number with priority listed for each group */Static voidSet_priority_group (U8 group_num) {U32 temp =0, Temp1 =0; Group_num = group_num% (sum_nvic_priotity_bits +1);//Because there are only 5 groups, so limit the numberTemp1 = ((~group_num) &0x07) <<8);//Reverse zone three-bit lowertemp = scb->aircr; Temp &=0x0000f8ff;//Clear 8-10-bitTemp |=0x05fa0000;//must write 5FA bit, is function as key, do not write words write the grouping is invalidTemp |= Temp1; SCB-&GT;AIRCR = temp;}/* Set Priority Group * G_priority: preemption priority sub_priority: Response priority * Irq_num: Interrupt number Prioritygroup: Priority Group */voidNvic_set_priority (U8 g_priority, U8 sub_priority, Irqn_type irq_num, U8 prioritygroup) {int32_t sub_priority_bits =0;    Sub_priority_bits = Sum_nvic_priotity_bits-prioritygroup; ASSERT (Sub_priority_bits >=0);//assertion, if the error is less than 0    / * Prototype #define ASSERT (x) while (!) ( x) {printf ("Assert failed!!!                             file:%s function:%s line:%d\r\n ", __file__, __function__, __line__);                             Delay_ms (1000); }    */Set_priority_group (Prioritygroup);//Set Priority grouping    / * Reference to Kernel header file * /    if(Irq_num <0)//To determine if less than 0 is the reason: the kernel header file is set to the core interrupt is less than 0 enumeration type, and the others are greater than 0, the reference kernel header file{/ * According to the SCB structure in the kernel header file corresponding to the kernel manual part of the calculation * /scb->shp[(uint32_t) (Irq_num) &0xF)-4] = ((g_priority << sub_priority_bits) | sub_priority) << (8-Sum_nvic_priotity_bits); }Else{nvic->ip[(uint32_t) (irq_num)] = ((g_priority << sub_priority_bits) | sub_priority) << (8-Sum_nvic_priotity_bits); }}/ * Enable the corresponding interrupt as required * /voidNVIC_ENABLE_IRQ (Irqn_type IRQ) {nvic->iser[(uint32_t) ((int32_t) IRQ) >>5] |= (uint32_t) (1<< ((uint32_t) ((int32_t) IRQ)% +));}voidEx_irq_config (gpiox_select gpiox,gpiox_pn_select gpiox_n,gpio_irq_trigger TRIGGER) {Rcc->apb2enr |= (1<< -);//Enable SYSCFG module, only the setting of the SYSCFG register will be valid after enablingGpio_init (Gpiox, Gpiox_n, Bym_pull_up, BYM_GPI, Bym_high_level, bym_push_pull);//Initialize GPIO as input, internal pull-upsyscfg->exticr[gpiox_n/4] &= ~ (0xF<< ((gpiox_n%4) *4));//syscfg->exticr[gpiox_n/4] |= (gpiox << (gpiox_n%4) *4));//Map px_n to Extin breakEXTI-&GT;IMR |= (1<< gpiox_n);//UnblockEXTI-&GT;RTSR |= (Trigger &0x01) << gpiox_n);//Set trigger alongEXTI-&GT;FTSR |= (Trigger >>1) << gpiox_n);}/ * Interrupt flag cleared only for external interrupts * /voidEx_irq_clear (U8 IRQ) {EXTI-&GT;PR |= (1<< IRQ);}

7, test and test preemption priority of different situations

Main program

NVIC_set_priority(122);NVIC_set_priority(212);EX_irq_config(BYM_GPIOE, BYM_Px3, IRQ_BOTHEDGE);EX_irq_config(BYM_GPIOE, BYM_Px2, IRQ_BOTHEDGE);NVIC_enable_irq(EXTI3_IRQn);NVIC_enable_irq(EXTI2_IRQn);

Interrupt Service Program

voidexti3_irqhandler (void){if (0 = = Gpio_get (Bym_gpioe, bym_px3)){printf ("Key 1 down \ r \ n");Delay_ms (+);printf ("Key 1 end \ r \ n"); }ex_irq_clear (3);} voidexti2_irqhandler (void){if (0 = = Gpio_get (Bym_gpioe, bym_px2)){printf ("Key 2 down \ r \ n");Delay_ms (+);printf ("Key 2 end \ r \ n"); }ex_irq_clear (2);}

Press GPE3 first (corresponding to EXTI3), immediately press GPE2 (corresponding to EXTI2), with the following output (will not be interrupted)

Key 1 Downkey 1 End

First press GPE2 (corresponding to EXTI2), immediately press GPE3 (corresponding to EXTI3), with the following output (EXTI2 interrupt was EXTI3 interrupted)

Key 2 down key 1 down key 2 EndKey 1 end

Cases where the same priority is tested for preemption and the response priority is different

The main program changes as follows

NVIC_set_priority(122);NVIC_set_priority(112);EX_irq_config(BYM_GPIOE, BYM_Px3, IRQ_BOTHEDGE);EX_irq_config(BYM_GPIOE, BYM_Px2, IRQ_BOTHEDGE);NVIC_enable_irq(EXTI3_IRQn);NVIC_enable_irq(EXTI2_IRQn);

Press GPE3 first (corresponding to EXTI3), immediately press GPE2 (corresponding to EXTI2), with the following output (will not be interrupted)

Key 1 Downkey 1 End

Press GPE2 first (corresponding to EXTI2), immediately press GPE3 (corresponding to EXTI3), with the following output (will not be interrupted)

Key 2 down key 2 end

8, the process of writing ideas

1. Set priority grouping, use SCB's AIRCR register (important is write key, 5FA)
2. Specifically plan for intra-group preemption and response prioritization, if the outage is kernel, use SCB 3. Control module, if it is external, use the NVIC module
3. Enable the SYSCFG module clock, map the corresponding middle line break, if it is an IO port interrupt also set the jump edge and initialize the IO Pin
4. Unblocking or event masking (Exti register)
5. Nvic enable the corresponding interrupt
6. Writing an interrupt service program

Interruption of STM32