Introduction to Axi Bus

0. Introduction

Axi is an advanced extension interface, which is presented in AMBA3.0 and AMBA4.0 its modifications to AXI4.0. AMBA4.0 including AXI4.0, Axi4.0-lite, ACE4.0, Axi4.0-stream

Axi4.0-lite is a simplified version of Axi, ACE4.0 is the Axi cache conformance extension interface, Axi4.0-stream is proposed by arm and Xilinx, mainly used in FPGA for data-driven, large data transmission applications.

1. Introduction

1.1 About the Axi protocol

The AMBA Axi protocol supports high-performance, high-frequency system design.

• Suitable for high bandwidth and low latency design
• High-frequency operation without complex bridges
• To meet the interface requirements of most devices
• Storage controller for high initial delay
• Flexibility and independence for an interconnected architecture
• Backwards compatible with existing AHB and APB interfaces

Key Features:

• Separated address/control, data phase
• Use byte lines to support non-aligned data transfers
• With burst-based transport, you only need to transfer the first address
• Separate read and write data channels to provide low power DMA
• Supports multiple addressing methods
• Support for disorderly transmission
• Allows easy addition of register levels for timing closure

1.2 Axi Architecture

The AXI protocol is a burst-based transmission and defines the following 5 independent transmission channels: Read address channel, read data channel, write address channel, write data channel, write response channel.

The address channel carries the control message to describe the transmitted data properties, the data transmission uses the write channel to achieve "master" to "from" the Transmission, "from" uses the write response channel to complete the write transmission; The Read channel is used to transmit data from "from" to "master".

Figure 1-1 Read schema

Figure 1-2 Writing the schema

Axi is a data transfer protocol based on the Valid/ready handshake mechanism, which uses valid to indicate that the address/control signal and data are valid, and that the destination uses ready to indicate that it can accept the information.

Read/write Address channel: Read, write the transmission each has its own address channel, the corresponding address channel carries the corresponding transmission address control information.

Read Data channel: The read data channel carries the read data and the read response signal including the bus data (8/16/32/64/128/256/512/1024bit) and the read signal indicating the completion of the read transmission.

Write Data channel: The data information of the write data channel is considered as buffering (buffered), and "master" can initiate a new write transfer without waiting for "from" the acknowledgement of the last write transmission. The Write channel includes the data Bus (8/16...1024bit) and byte lines (to indicate the validity of the 8bit data signal).

Write response channel: "From" uses the write response channel to respond to the write transmission. All write transmissions need to write the completion signal of the response channel.

Figure 1-3 Interface and interconnect

The AXI protocol provides a single interface definition that can be used between the following three interfaces: Master/interconnect, Slave/interconnect, Master/slave.

You can use the following typical system topology architectures:

• Shared address and data bus
• Shared address bus, most data bus
• Multilayer multilayer, multi-address bus, mostly bus

In most systems, the bandwidth requirements for address channels are not high for data channels, so you can use shared address bus, which balances system performance and interconnect complexity with a majority of bus architectures.

Register chip (register Slices):

Each AXI channel transmits information in a single direction, and each channel has no fixed relationship directly. The register slice can therefore be inserted at any point in any channel, which, of course, results in additional cycle delays.

The use of register slices allows for a tradeoff between the cycle delay (cycles of latency) and the maximum operating frequency, and the use of register slices to split the long path of low-speed peripherals.

2. Signal description

Table 2-1 Global Signals

Signal Name	Source	Describe
Aclk	Clock source	Global Clock signal
Aresetn	Reset Source	Global reset signal, low effective

Table 2-2 write address channel signal

Signal Name	Source	Describe
AWID	Host	Write address ID, used to flag a set of write signals
Awaddr	Host	Write address, give a write address of the burst transmission
Awlen	Host	Burst length, given the number of burst transmissions
Awsize	Host	Burst size, given the number of bytes per burst transmitted
Awburst	Host	Burst type
Awlock	Host	Bus lock signal to provide operational atomicity
Awcache	Host	The type of memory that indicates how a single transmission passes through the system
Awprot	Host	Protection type, indicating the privilege level and security level of a single transmission
Awqos	Host	Quality service QoS
Awregion	Host	A zone flag that enables multiple logical interfaces for a single physical interface
Awuser	Host	User-defined signals
Awvalid	Host	A valid signal indicating that the address control signal for this channel is valid
Awready	Slave machine	Indicates "from" can receive address and corresponding control signal

Table 2-3 Write Data channel signal

Signal Name	Source	Describe
Wid	Host	ID of the one-time write transfer tag
Wdata	Host	Write Data
Wstrb	Host	Write data valid byte line to indicate which 8bits data is valid
Wlast	Host	Indicates that this transmission is the last burst transmission
Wuser	Host	User-defined signals
Wvalid	Host	Write valid, indicating that this write is valid
Wready	Slave machine	Indicates that the slave can receive write data

Table 2-4 Write response channel signal

Signal Name	Source	Describe
BID	Slave machine	Write Response ID Tag
Bresp	Slave machine	Write response indicating the state of the write transmission
Buser	Slave machine	User definable
Bvalid	Slave machine	Write response Valid
Bready	Host	Indicates that the host is able to receive write responses

Table 2-5 read Address channel signal

Signal Name	Source	Describe
Arid	Host	Read address ID, used to flag a set of write signals
Araddr	Host	Read address, give the read address of a write burst transmission
ARLEN	Host	Burst length, given the number of burst transmissions
Arsize	Host	Burst size, given the number of bytes per burst transmitted
Arburst	Host	Burst type
Arlock	Host	Bus lock signal to provide operational atomicity
Arcache	Host	The type of memory that indicates how a single transmission passes through the system
Arprot	Host	Protection type, indicating the privilege level and security level of a single transmission
Arqos	Host	Quality service QoS
Arregion	Host	A zone flag that enables multiple logical interfaces for a single physical interface
Aruser	Host	User-defined signals
Arvalid	Host	A valid signal indicating that the address control signal for this channel is valid
Arready	Slave machine	Indicates "from" can receive address and corresponding control signal

Table 2-6 read Data channel signals

Signal Name	Source	Describe
RID	Slave machine	Read ID Tag
RDATA	Slave machine	Read data
Rresp	Slave machine	Read response, indicating the state of the read transmission
Rlast	Slave machine	Indicates the last transmission of a read burst
Ruser	Slave machine	User definable
Rvalid	Slave machine	Indicates that this channel signal is valid
Rready	Host	Indicates that the host is able to receive read data and response information

Table 2-7 low-power Interface signals

Signal Name	Source	Describe
Csysreq	Clock Controller	The system exits the low-power request, which is from the "clock controller" to the "peripheral"
Csysack	Peripherals	Exit Low power status acknowledgement
Cactive	Peripherals	Peripheral request Clock is valid

3. Signal Interface Requirements

3.1 Clock Reset

Clock

Each AXI component uses a clock signal aclk, all input signals are sampled on the ACLK rising edge, and all output signals must occur after the rising edge of the ACLK.

Reset

Axi uses a low-level, effective reset signal ARESETN, which can be asserted asynchronously, but must be synchronized with the clock rising edge to assert.

During the reset, the interface has the following requirements: The ① host interface must drive the Arvalid,awvalid,wvalid low level, the ② slave interface must drive Rvalid,bvalid to low level, ③ all other signals can be driven to any value.

After the reset, the host can drive the arvalid,awvalid,wvalid on the rising edge of the clock to a high level.

3.2 Basic read/write transmission

Handshake process

All 5 transmission channels use the valid/ready signal to shake the address, data, and control signals of the transmission process. With a two-way handshake, the transfer occurs only when the valid, ready and valid. are several handshake mechanisms:

Figure 3-1 VALID before ready handshake

Figure 3-2 Ready before VALID handshake

Figure 3-3 VALID with ready handshake

Channel Signal requirements

Channel handshake signal: Each channel has its own xvalid/xready handshake signal pair.

Write Address channel: When the host drives a valid address and control signal, the host can assert awvalid, and once asserted, it is necessary to maintain the Awvalid assertion state until the clock rises along the sampling to the slave's awready. Awready The default value can be high or low, recommended high (if low, a transmission requires at least two cycles, one to assert awvalid, one to assert Awready), and when Awready is high, the slave must be able to accept the valid address provided to it.

Write Data channel: During the write burst transmission, the host can only assert wvalid when it provides valid write data, and once asserted, the assertion state needs to be maintained, knowing that the clock is rising along the sampling to the slave's wready. The Wready default value can be high, which requires the slave to always be able to accept write data within a single cycle. The host is required to assert the wlast signal when driving the last write burst.

Write response channel: Slave can only assert bvalid when it drives a valid write response, once the assertion needs to be persisted until the clock rises along the bready signal that is sampled to the host. The default value of Bready can be set to high when the host always accepts a write response signal in a cycle.

Read Address channel: When the host drives a valid address and control signal, the host can assert arvalid, and once asserted, it is necessary to maintain the Arvalid assertion state until the clock rises along the sampling to the slave's arready. Arready The default value can be high or low, recommended high (if low, a transmission requires at least two cycles, one to assert arvalid, one to assert Arready), and when Arready is high, the slave must be able to accept the valid address provided to it.

Read Data channel: The slave can assert rvalid only when the slave is driving valid read data, and once the assertion needs to be persisted until the clock rises along the bready that is sampled to the host. The bready default value can be high, at which time the host needs to read the data as soon as it starts reading the transmission. When the last burst reads the transmission, the slave needs to assert the rlast.

Inter-channel relationships

The AXI protocol requires that the following relationships be met between channels:

• Write response must follow the last write transmission of burst
• Read data must follow the corresponding address of the data
• The channel handshake signals need to confirm some dependency resistance

On-resistance relationship of channel handshake signal

To prevent deadlocks, channel handshake signals need to follow a certain dependency. The ①valid signal cannot be in accordance with the ready signal. The ②axi interface can wait until the valid is detected to assert the corresponding ready, or it can detect valid before it is asserted to ready. Here are a few figures showing that a single-arrow-pointing signal can be asserted before or after the arrow start signal, depending on the resistance, and the signal pointed by the double arrow must be asserted after the arrow start signal assertion.

Figure 3-4 Read transfer handshake dependency resistance

Figure 3-5 Write transfer handshake dependency resistance

Figure 3-6 Slave-write response handshake dependency resistance

3.3 Transmission Structure

Address structure

The AXI protocol is based on burst, and the host only gives the address of the first byte of the burst transmission, from which the machine must calculate the subsequent address of the burst. Bursts cannot span 4KB boundaries (preventing bursts from crossing the boundary of two slave machines, and also limiting the number of address self-increment required to be supported by the slave).

1) Burst length

ARLEN[7:0] Determines the burst length of the read transmission, awlen[7:0] determines the burst length of the write transmission. AXI3 only supports 1~16 bursts (burst_length=axlen[3:0]+1), AXI4 extended burst length support incr burst type 1~256 secondary transmission, and for other transport types remains 1~16 burst (burst_length =axlen[7:0]+1).

The burst transport has the following rules:

• Wraping burst, burst length must be 2,4,8,16
• Burst cannot span 4KB boundaries
• Early termination of burst transmission is not supported

All components cannot prematurely terminate a burst transmission. However, the host can reduce the number of write transfers by asserting all of the written strobes to make non-all writing sections. Read burst, the host can ignore the subsequent reading data to reduce the number of reads. In other words, all burst transmissions must be done anyway.

Note: For FIFO, ignoring subsequent read data can result in data loss, which must be guaranteed to match the burst length and the required data transfer size.

Burst size

ARSIZE[2:0], read burst transmission; awsize[2:0], write burst transmission.

Axsize[2:0] Bytes in transfer

' b000 1

' B001 2

' B010 4

' b011 8

' B100 16

' B101 32

' B110 64

' b111 128

Burst type

Fixed: fix address during burst transmission, for FIFO access

INCR: Incremental burst, during transmission, address increment. The amount of increase depends on the value of Axsize.

WRAP: A loopback burst, similar to an incremental burst, but returns to a low address at a specific high address boundary. The length of a loopback burst can only be 2,4,8,16, and the first address of the transmission and the size of each transmission are aligned. The lowest address is aligned across the data size of the transmission. The loopback boundary is equal to (Axsize*axlen).

AXBURST[1:0] Burst type

' B00 FIXED

' B01 INCR

' B10 WRAP

' B11 Reserved

Start_address=axaddr

Number_bytes=2^axsize

Burst_length=axlen+1

Aligned_addr= (INT (start_address/number_bytes)) xnumber_bytes. int means rounding down.

For incr bursts and wrap bursts but does not reach the loopback boundary, the address is determined by the following equation:

address_n=aligned_address+ (N-1) xnumber_bytes

Wrap burst, burst boundary:

Wrap_boundary= (INT (start_address/(number_bytes x Burst_length)) x (Number_bytes x burst_length)

Data reading and writing structure

WSTRB[N:0] corresponds to the corresponding writing section, Wstrb[n] corresponds to wdata[8n+7:8n]. When the wvalid is low, WSTRB can be any value, Wvalid is high, byte lines with a high WSTRB must indicate valid data.

Narrow transmission

When a host produces a transmission that is narrower than its data bus, the address and control signal determine which byte is transmitted:

INCR and wrap, different byte lines determine the data that each burst transmits, FIXED, and each transmission uses the same byte line.

5 bursts are given, the starting address is 0, each transmission is 8bit, the data bus is 32bit, and the burst type is incr.

Figure 3-7 Example of narrow transmission 1

Give 3 bursts, the starting address is 4, each transmission 32bit, the data bus is 64bit.

Figure 3-8 Example of narrow transmission 2

Non-aligned transport

Axi supports non-aligned transports. In a transmission larger than one byte, the first own transmission may be non-aligned. such as 32-bit packet start address in 0x1002, non-32bit aligned.

The host can ① use a low-level address line to represent a non-aligned starting address, ② provides a starting address for alignment, and a byte line to represent a non-aligned starting address.

Figure 3-9 Example of Qife alignment transfer 1-32bit bus

Figure 3-10 Example of Qife alignment transfer 2-64bit bus

Figure 3-11 Example of an aligned loopback transport

Read-Write response structure

The response information for the read transmission is attached to the read data channel, and the write-transmit response is in the write-response channel.

RRESP[1:0], read transfer

BRESP[1:0], write transfer

OKAY (' b00): normal access successful

Exokay (' B01): Exclusive Access Successful

Slverr (' B10): Slave error. Indicates that the access has succeeded to the slave, but the slave wants to return an error condition to the host.

Decerr (' B11): decoding error. Generally given by the interconnect component, indicating that there is no corresponding slave address.

Introduction to Axi Bus