Introduction to SPI Bus

SPI Bus Structure

The SPI (Serial peripheral Interface) Serial Peripheral Interface is a high-speed, full-duplex, synchronous communication bus. The Master Slave architecture is used to support multiple Slave, generally supporting only single master.

There are 4 signal lines in the SPI interface, namely: Device Selection Line (SS), clock Line (SCK), serial output data cable (MOSI), serial input data cable (miso).

Data transfer process:

The master node outputs data through the MOSI (master output Slave input) line from the node in SIMO (Slave input Master output) read data from the master node. At the same time, the MSB (highest bit) is output through Somi (Slave output master input) , and the master node is in miso (Master input Slave output) reads the data from the node, and the entire process continues until all data is exchanged.

Bus timing

Cpol Polarity: Determines whether the clock is high or low when idle
CPOL=0:CLK is low when idle, high when CLK is active
CPOL=1:CLK is high when idle, low level when CLK is active

Cpha phase: Determines when data is sampled (read)
Cpha=0: First Edge sampling
Cpha=0: First Edge sampling

SPI is divided into 4 modes according to the different combinations of Cpol and Cpha

Introduction to SPI Bus