1 JTAG (joint test action group; joint test action group) is an international standard test protocol (IEEE 1149.1 compatible) used for internal chip testing. Most advanced devices now support the JTAG protocol, such as DSP and FPGA Devices. The standard JTAG interfaces are four lines: TMS, tck, TDI, and TDO, which are the mode selection, clock, data input, and data output lines respectively.
JTAG was initially used to test the chip. The basic principle of JTAG is to define a Test Access Port (Test Access Port) inside the device) use a dedicated JTAG test tool to test internal nodes. JTAG testing allows multiple devices to be connected together through the JTAG interface to form a JTAG chain, which can be used to test each device separately. Currently, the JTAG interface is often used to implement ISP (in-system programmable & #0; online programming) and program flash and other devices.
The JTAG programming method is online programming. In the traditional production process, the chip is pre-programmed and then installed on the board. Therefore, the simplified process is fixed to the board and then programmed with JTAG, this greatly accelerates the project progress. The JTAG interface can be used to program all components inside the PSD Chip.
All chips with JTAG ports have the following JTAG pin definitions:
TCK -- test the clock input;
TDI-test data input. Data is input through the JTAG port of TDI;
TDO -- test data output, which is output from the JTAG port through TDO;
TMS-test mode selection. TMS is used to set the JTAG port to be in a specific test mode.
Optional pin trst -- Test reset, input pin, low level valid.
There are many types of chips including JTAG ports, such as CPU, DSP, and CPLD.
The JTAG has a state machine called the TAP controller. The state machine of the TAP controller changes the status through TCK and TMS to input data and commands. Figure 1 shows the state machine diagram of the TAP controller.
2. JTAG chip Boundary Scan register
The JTAG Standard defines a serial shift register. Each unit of the Register is assigned to the corresponding pins of the IC chip. Each independent unit is called the boundary-scan cell boundary scanning unit. This series of BSC forms a JTAG loop within the IC. All BSR (Boundary-scan register) boundary scan registers are activated through the JTAG test. These pins maintain normal IC functions. Figure 2 shows the relationship between BSR units and pins in an IC with a JTAG port.
3 JTAG hardware circuit design for online flash writing and connection with PC
Taking strongarm sa1110 with the JTAG interface as an example, flash provides intel 28f128j32 16 MB capacity. The jtag tck, TDI, TMS, and TDO of sa1110 are connected to the ports 2, 3, 4, and 11 of the same PC respectively.ProgramControl commands and targets for the JTAG PortCodeWrite Data from the parallel port of the PC to the BSR of the JTAG. When designing a PCB, the sa1110 data line and address line and control line must be connected to the Flash earth line, data line and control line. Because the corresponding BSC exists on the pins of the sa1110 data line, address line, and control line, as long as the JTAG command is used to send the data, address and control signal to the BSC, the signal can be sent to flash through the corresponding pin of the BSC to implement flash operations. The JTAG system board design and connection relationship are shown in figure 3.
4. Use the commands of the TAP State Machine to perform flash operations.
By setting TCK and TMS, you can set the JTAG to the receiving command or data status. Common JTAG commands are as follows:
Sample/preload -- Use this command to sample the BSC content or write data to the BSC unit;
Extest -- when this command is executed, the BSC content is sent to the pins of the corresponding chip connected to it through the pins. We use this command to write flash online;
Bypass -- this command places a register in the BSC's shift loop, that is, only one register is located between TDI and TDO.
After the PCB circuit is designed, you can use a program to first send control commands on JTAG to the command register of the JTAG controller through TDI. Then, use TDI to write the flash Address, data, and control line signals to BSR, lock the data to the BSC, and use the extest command to write the data to flash through the BSC.
5. Software Programming
The Program for online flash writing is written in Turbo C. The program uses the parallel port of the PC to write the program into the flash chip through the chip containing the JTAG. The program first initializes the parallel port of the PC, resets and tests the JTAG port, and reads flash to determine whether to lock the port. If the lock is applied, you must unlock it before you can perform the operation. Before writing flash, you must erase it first. Set the JTAG chip in extest mode, write the target file to flash through JTAG through the parallel port of the PC, and verify the file after the download is completed. The main procedure 4 is shown in.
The subprogram of the read chip ID through JTAG is as follows:
Void id_command (void ){
Putp (, ip); // run-test/idle; reset JTAG
Putp (1, 0, ip); // run-test/idle
Putp (1, 0, ip); // run-test/idle
Putp (1, 0, ip); // run-test/idle
Putp (1, 1, ip );
Putp (, ip); // select the instruction register
Putp (, ip); // capture command register
Putp (1, 0, ip);/shift instruction register
Putp (01100, ip); // The length of the sa1110jtag command is 5 bits, and the idcode is
Putp (1, 0, ip );
Putp (1, 0, ip );
Putp (0, 0, ip );
Putp (0, 0, ip );
Putp (0, 1, ip); // exit the instruction register
Putp (, ip); // update the instruction register and execute the instruction in the instruction register
Putp (1, 0, ip); // run-test/idle
Putp (1, 0, ip); // run-test/idle
Putp (1, 0, ip); // run-test/idle
Putp (1, 1, ip );
Putp (1, 0, ip );
If (check_id (sa1110id ))
Error_out ("failed to read device ID for the SA-1110 ");
Putp (, ip); // exit the data register
Putp (, ip); // update the data register
Putp (, ip); // run-test/idle to reset the JTAG
Putp (1, 0, ip); // run-test/idle
Putp (1, 0, ip); // run-test/idle
}
6 precautions for circuit design and programming
① The we, Ce, OE and other control lines of Flash chips must be connected to the sa1110 BSR. Only in this way can the flash pins be controlled through BSR.
② The connection line between the JTAG port and the PC port should be as short as possible. In principle, the connection line should not exceed 15 cm.
③ Flash requires a large amount of operating current when writing and programming. It must be considered when selecting the power supply chip of the system.
④ To improve the programming speed of flash, try to make TCK no less than 6 MHz, You can compile the Flash program.
(Source: Embedded Online Forum)