Introduction to MII, gmii, and rmii Interfaces

MII (Media independent interface)

MII is the media independent interface, which is the Ethernet industry standard defined by the IEEE-802.3. It includes a data interface and a management interface between MAC and PHY (figure 1 ). The data interface includes two independent channels used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal. The MII data interface requires a total of 16 signals. The management interface is a dual-signal interface: one is the clock signal, and the other is the data signal. Through the management interface, the upper layer can monitor and control the phy. The MII management interface has only two signal lines. The configuration and status data is written/read to/from the PHY via the mdio signal.

The MII standard interface is used to connect Fast Ethernet MAC-block and PHY. "Media Independence" indicates that any type of PHY device can work properly without re-designing or replacing the Mac hardware. Interfaces working at other speeds are equivalent to MII: AuI (10 M Ethernet), gmii (Gigabit Ethernet), and xaui (10-Gigabit Ethernet ).

MII Bus

The MII bus specified in 802.3 is a universal bus used to connect different types of PHY to the same network controller (MAC. The network controller can use the same hardware interface and

 

Gmii (Gigabit MII) Gmii uses eight-bit interface data with a 125 MHz clock, so the transmission rate can reach 1000 Mbps. It is also compatible with the MII 10/100 Mbps working mode. The gmii interface data structure complies with the IEEE Ethernet standard. For the interface definition, see IEEE 802.3-2000. Transmitter: ◇ Gtxclk -- the clock signal of the guitar TX .. signal (125 MHz) ◇ TXCLK--10/M signal clock ◇ Txd [7 .. 0] -- sent data ◇ Txen-transmitter enabling Signal ◇ Txer -- transmitter error (used to destroy a data packet) Note: gtxclk signals are provided to PHY at a gigabit rate. txd, txen, and txer signals are synchronized with these clock signals. Otherwise, at a rate of 10/100 M, phy provides the txclk clock signal, and other signals are synchronized with this signal. The operating frequency is 25 MHz (2.5 m Network) or MHz (10 m network ). Receiver: ◇ Rxclk -- receives the clock signal (extracted from the received data, so it is not associated with gtxclk) ◇ Rxd [7 .. 0] -- receives data ◇ Rxdv -- receive valid data indication ◇ Rxer -- receive Data Error Indication ◇ Col-conflict detection (for half duplex only) Manage configurations ◇ MDC -- configure the interface clock ◇ Mdio -- configure the interface I/O Manage the configuration interface to control the features of the phy. This interface has 32 register addresses, each of which is 16 bits. Among them, the first 16 have defined the purpose in "IEEE 802.3, 2000-22.2.4 management functions", and the remaining are designated by each device.

 

Rmii: reduced media independant Interface

Simplified independent media APIs

It is one of the standard Ethernet interfaces and has less I/O transmission than MII.

Questions about rmii and MII

The rmii port uses two wires to transmit data,

The MII port uses four wires to transmit data,

Gmii uses eight wires to transmit data.

MII/rmii is only an interface. For 10 m wire speed, the MII speed is 2.5 m, and rmii is 5 M. For M wire speed, the MII speed is 25 m, rmii is 50 m.

MII/rmii is used to transmit Ethernet packets. The MII/rmii interface is 4/2bit, in the Ethernet phy, serial and encoding/decoding must be performed to transmit data to twisted pair wires and optical fiber cables. The frame format complies with IEEE 802.3 (10 m)/IEEE 802.3u (100 m) /IEEE 802.1Q (VLAN ).

The format of the Ethernet frame is: prefix + start bit + Destination MAC address + source MAC address + type/Length + Data + padding (optional) + 32 bitcrc

If a VLAN exists, a two-byte VLAN tag is added after the type/length. 12 bits represent the vlan id, and 4 bits represent the data priority!

RJ45 interface signal definition and network connection head signal Arrangement

Ethernet 10/100 BASE-T interface:
Pin Name Description
1 Tx + tranceive Data + (sending signal +)
2 TX-tranceive data-(sending signal -)
3 RX + receive data + (receiving signal +)
4 N/C not connected (empty foot)
5 N/C not connected (empty foot)
6 RX-receive data-(receiving signal -)
7 N/C not connected (empty foot)
8 N/C not connected (empty foot)

Ethernet 100base-t4 interface:
Pin Name Description
1 tx_d1 + tranceive Data +
2 tx_d1-tranceive data-
3 rx_d2 + receive data +
4 bi_d3 + bi-directional Data +
5 bi_d3-bi-directional data-
6 rx_d2-receive data-
7 bi_d4 + bi-directional Data +
8 bi_d4-bi-directional data-
T568b: 8-pin/8-wire white orange, orange, white green, blue, white blue, green, white brown, brown
T568a: 8-pin/8-wire white green, green, white orange, blue, white blue, orange, white brown, brown

 

Ethernet is a computer LAN networking technology based on the IEEE 802.3 standard. It specifies the contents of the physical layer connections, electrical signals, and media access layer protocols. Ethernet is currently the most widely used LAN technology. It largely replaces other LAN standards, such as the licensing ring, FDDI, and ARCNET. After the rapid development of M Ethernet at the end of the last century, Gigabit Ethernet and even 10G Ethernet are continuously expanding their application scope under the impetus of international organizations and leading enterprises. Ethernet-based applications have been a research and development hotspot for a certain period of time.

 

Ethernet interfaces are essentially the process in which Mac controls the PHY through the MII bus.

 

Mac is short for media access control, that is, the sub-layer protocol of media access control. The Protocol is located in the lower half of the data link layer in the OSI Layer 7 protocol and is mainly responsible for controlling and connecting physical media of the physical layer. When sending data, the MAC protocol can determine whether data can be sent in advance. If data can be sent, it adds some control information to the data, and finally sends the data and control information to the physical layer in the specified format; when receiving data, the MAC protocol first checks the input information and determines whether a transmission error has occurred. If there is no error, the control information is removed and sent to the LLC layer. Ethernet MAC is defined by IEEE-802.3 Ethernet standards.

 

MII is an independent media interface. "Media Independence" indicates that any type of PHY device can work normally without re-designing or replacing Mac hardware. Two independent channels are used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal. The MII data interface requires a total of 16 signals, including tx_er, txd <:0>, tx_en, tx_clk, Col, rxd <:0>, rx_ex, rx_clk, CRS, and rx_dv.

MII transmits data in four-byte bidirectional transmission with a clock rate of 25 MHz. The working rate can reach 100 Mb/s. The MII management interface is a dual-signal interface. One is a clock signal and the other is a data signal. Through the management interface, the upper layer can monitor and control the phy. Its management is implemented by using the SMI (Serial Management Interface) bus to read and write the register of the phy. Some registers in the PHY are defined by IEEE. In this way, the PHY reflects its current status to the Register, mac constantly reads the Status Register of the PHY through the SMI bus to get the current PHY status, such as connection speed and duplex capability. Of course, you can also set the register of the PHY through SMI to achieve the purpose of control. For example, if the throttling is enabled or disabled, the self-negotiation mode or the forced mode can be used. Both the MII bus for physical connection and the State registers and control registers for the SMI bus and the PHY have IEEE specifications. Therefore, the Mac and the PHY of different companies can coordinate their work. Of course, in order to match the features specific to PHY of different companies, the driver needs to be modified accordingly.

Phy is a physical interface transceiver that implements the physical layer. Including the MII/gmii (Media independent interface) Sub-layer, PCs (physical encoding sub-layer), PMA (physical media attachment) Sub-layer, PMD (physical media-related) Sub-layer, and MDI sub-layer.

100basetx adopts 4b/5b encoding. When sending data, phy receives data from MAC (for phy, there is no frame concept, and for it, it is data regardless of the address, data or CRC ), an Error Code of 1 bit is added for every 4 bits. Then, parallel data is converted into serial stream data, and the data is encoded according to the encoding rules of the physical layer. Then, the data is sent as a analog signal. Otherwise. Another important feature of PHY is to implement some CSMA/CD functions. It can detect whether data is being transmitted on the network. If data is being transmitted, it waits. Once it detects that the network is idle, it waits for a random time and sends the data out. If the two send data at the same time, a conflict will occur. At this time, the conflict detection agency can detect the conflict and wait for a random time to resend the data. This random time is very exquisite. It is not a constant. The random time calculated at different times is different, there are multiple algorithms to cope with the second conflict between the two hosts with low probability. The communication rate is negotiated by both parties. The negotiation result is the maximum speed and the best duplex mode supported by both devices at the same time. This technology is called auto negotiation or Nway. The isolating transformer filters the differential signals sent from the PHY using the differential mode coupled coils to enhance the signal, and couple the signals to the other end of the connected network through the electromagnetic field conversion. In the RJ-45, 1, 2 are the data, and 3, 6 are the data. The new PHY supports the auto MDI-X feature (also requires isolation transformer support ). It can realize the transfer signal line on 1 and 2 of RJ-45 interface and the function of receiving signal line on 3 and 6 automatically exchange with each other.