Introduction to SPI Bus

1. Introduction

SPI, Serial peripheral Interface, Serial Peripheral interface, is a high-speed, full-duplex, synchronous communication bus
SPI occupies only four wires on the chip's pins

SPI interface is mainly used for MCU and various peripheral devices to communicate in a serial way to exchange information
Peripherals include EEPROM, FLASH, real-time clock, ad converter, digital signal processor, and digital signal decoder

It works in a master-slave manner, usually with one main device and one or more slave devices
are two common scenarios for SPI

2. Signal Line

SPI typically has four signal lines

-SCLK      : Serial Clock (from master output)-Mosi/simo:master output, Slave input (from master output)-Miso/somi:master input, Slave O Utput (self Slave output)-SS        : Slave Select (active low; self-master output)

Another type of salutation is widely used

-SCK            : Serial Clock (from master output)-Sdi/di/si      : Serial data in-sdo/do/so      : Serial data out-ncs/cs/nss/ste: Chip Select, Slave transmit Enable (low active; self-master output)

3. Working principle

In the SPI, the data is sent and received synchronously, and the clock of the data transfer is based on the clock pulse from master
The most commonly used clock settings are based on the clock polarity (CPOL) and clock phase (CPHA), which determine the clock edge of the data sampling
-Clock Polarity (CPOL): Defines the active state of the SPI serial clock,
Cpol=0 indicates that the clock start value is low, so the first stage (front) is on the rising edge and the second stage (back edge) is the falling edge
The cpol=1 indicates that the clock is starting to be high, so the first stage (front) is the falling edge;
-Clock phase (CPHA): Defines the clock phase relative to the data bit for sampling data,
Cpha=0 indicates sampling during the cutting-edge period; Cpha=1 indicates sampling at the back edge

tip: For Cpol and Cpha, please refer to < detailed description of polarity Cpol and phase cpha in SPI >

The combination of SPI based on Cpol and Cpha has four modes of operation

4. Timing Diagram

Time series diagrams are different in different modes of operation, but this is device-dependent, not described here

Reference
<SPI Subsystem Analysis >
<spi Block Guide v3>
< flash> in embedded devices

Introduction to SPI Bus