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∑– analog-to-digital converter (ADC)
In recent years, with the improvement of VLSI manufacturing level, sigma-Delta analog-to-digital converter is widely used for its high resolution , Good linearity and low cost . Sigma-Delta Analog-to-digital converters the proposal was already made in the 1960s, however, until recently, this process was not feasible in the production of devices commercially. Today, with the maturity of 1 micron technology and smaller CMOS geometries, Sigma-Delta analog-to-digital converters will increasingly appear in a number of specific application areas. In particular, in mixed-signal ICS (Mixed-signal ICS, which refer to integrated circuit chips with analog-to-digital converters, D/A converters, and DSP functions in a single chip). At present, Sigma-Delta analog-to-digital converters are mainly used for high-resolution mid-and low-frequency (low to DC) measurement and audio circuits. Typical chips for low-frequency measurements have 16-bit resolution AD7701,24-bit resolution AD7731, etc., and typical chips for high-quality digital audio applications have 18-bit resolution AD1879. With the improvement of design and process level, a high speed sigma-Delta analog-to-digital converter has been developed. such as AD7723 (1.2MSPS), AD9260 (2.5MSPS) and so on.
The theoretical basis of the 2.∑– type ADC
Unlike the General ADC, the∑– ADC is not quantified directly based on the size of each sample value of the sampled data, but rather on the size of the difference between the previous measure and the latter value, the so-called increment .
Quantitative coding. In a sense, it is quantified and encoded according to the envelope of the signal waveform. The ∑– ADC consists of two parts, the first part is the analog ∑– modulator and the second part is a digital decimation filter, as shown in.
The ∑– modulator samples the input analog signal at a very high sampling frequency and quantifies the difference between the two samples, thus obtaining a digital signal that is represented by a low-level digital ∑– code; and then this ∑– To the second part of the digital decimation filter for decimation filtering, resulting in high resolution
Rate of the linear pulse code modulated by the digital signal. So the decimation filter is actually the equivalent of a code-based converter. Because the ∑– modulator has a very high sampling rate, it is usually higher than the Nyquist sampling frequency
Many times, so the ∑– modulator is also known as Oversampling ADC Converter. This type of ADC uses a very low quantizer, which avoids the difficulty of making high-level converters and high-precision resistor networks, and because it uses ∑– modulation and digital decimation filtering to achieve very high resolution, and because of the low quantization output ∑– code, will not be sensitive to the magnitude of the sampling value, and because of the low code position, sampling and quantization coding can be completed at the same time, almost no time, so no need to sample and hold the circuit, which makes the composition of the sampling system greatly simplified. This kind of incremental modulation ADC is actually in exchange for high-speed sampling rate for high quantization, that is, speed to change the accuracy.
from the point of view of modulation coding theory, most traditional ADCs, such as parallel comparison, successive approximation, etc., belong to the linear pulse coded modulation (Lpcm,linear pulse code modulation) type. These ADCs are quantized encoded according to the magnitude of the signal, and the full scale level of the ADC with a resolution bit n is divided into 2n different quantization levels, in order to differentiate between the 2n A different quantization level requires a fairly complex resistor (or capacitor) network and high-precision analog electronic devices. When the number of bits n is high, it is difficult to compare the implementation of the network, thus limiting the converter resolution. At the same time, due to the influence of the integration and temperature ratio of the high-precision die-like electronic devices, the converter resolution is further limited.
Unlike the traditional LPCM ADC, the ∑– ADC is not quantized encoded directly according to the amplitude of the signal, but rather based on the difference between the previous sample value and the latter sample value (the so-called increment) of the quantization code, which in a sense is based on the envelope shape of the signal. From this point of view, it is a bit similar to the trace-count ADC.
Represents an increment, ∑ represents an integral or summation. As can be seen below, the ∑– ADC uses a very low-level quantizer (typically 1-bit), which avoids many of the difficulties encountered by the LPCM ADC in manufacturing and is ideally suited for MOS technology. On the other hand, because of its extremely high sampling rate and ∑– modulation technology, it can obtain very high resolution. At the same time, because it uses low-level quantization, it will not be too sensitive to the amplitude change of the input signal as the LPCM ADC.
Compared to a conventional LPCM ADC, the ∑– ADC is actually a high-sampling rate for higher quantization, which is a rate-for-resolution solution.
Oversampling (oversampling) technology is one of the many techniques to improve the overall performance of A/D converters. The ADC of the ∑-structure is an intrinsic oversampling converter. The ∑-ADC digitize analog signals at very low sample resolution (1-bit) and at very high sampling rates, using oversampling, noise shaping and digital filtering techniques to increase effective resolution, and then extract (decimation) the ADC output to reduce the effective sampling rate of the ADC, Eliminate redundant information and reduce the burden of data processing. Because of the good linearity of the 1-bit quantizer (1-bit comparator) and 1-bit digital-to-analog converters (∑-) used in the ADC, the differential linearity and integral linearity performance of the ∑-ADC is excellent, and unlike other types of ADCs, it does not require any trimming.
3. Fundamentals of first-order ∑– ADC
To understand how the ∑-ADC works, you must be familiar with several basic concepts such as sampling, noise shaping, digital filtering, and sampling extraction. The first-order ∑-ADC contains a very simple analog circuit (a comparator, a switch, one or several integrators and analog summing circuits) and a very complex digital signal processing circuit.
Sigma-Delta converters have a relatively simple structure, also known as oversampling converters. The converter consists of a σ-δ modulator (in a dashed box) and a digital filter attached to it. The structure of the modulator is very similar to the dual-slope ADC, comprising an integrator and a comparator, as well as a feedback loop containing a 1-bit ADC. This built-in DAC is just a switch that switches the integrator input to a positive or negative reference voltage. The σ also includes a clock unit that provides the appropriate timing for the modulator and digital filter.
is the input vin=0 and VIN=+VREF/4 two cases, the voltage waveform of each point in the circuit. You can see that in both cases, the number of "0" and "1" in the code stream of the C-point output is not the same.
The narrowband signal is fed into the σ and is quantified at very low resolution (1-bit), but the sampling frequency is very high, such as 2MHz or higher. After digital filtering, this oversampling is reduced to a relatively low sample rate, such as around 8KHz, while the resolution (i.e. dynamic range) of the ADC is increased to 16 bits or higher, although slower than the pipelined ADC and limited to the lower input bandwidth, This sigma-Delta technology still occupies an important position in the analog-to-digital converter market. It has three main advantages:
Low price, high performance (up to 24 bits)
Integrated Digital filtering
Compatibility with DSP technology for easy system integration
Mainly used in: Audio and measurement
Chip Example : ADS1210 series: 24-bit A/D converter. Burr-brown Corp.
In recent years, the use of high-resolution Sigma-Delta ADC is popular, it is a prominent advantage of a mixed-signal CMOS integrated circuit to achieve the combination of ADC and digital signal processing technology. Other advantages of this technology: a resolution of up to 24 bits, a higher conversion rate than an integral and a voltage-frequency conversion ADC, a mixed-signal CMOS process for low-cost, high-resolution data acquisition and digital signal processing; The requirement to filter the sensor signal is reduced, and the signal conditioning is actually canceled. disadvantage : high-order modulator is required when high-speed conversion, and higher power consumption than integral and successive-approximation ADCs under the same conversion rate.
Currently,Sigma-Delta ADC is divided into four categories: (1) high-speed ADC, (2) Modem class ADC, (3) Encoder class ADC, (4) sensor low-frequency measurement ADC. Each type of σ-δ ADC is divided into many models, which brings great convenience to users.
Introduction to ∑– analog-to-digital converters (ADCs)
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