Introduction to the architecture of TI C66787 multi-core DSP

The tms320c6678 is a 8-core DSP processor for the Keystone Architecture , with a frequency of up to 1.25 GHzper Corepac core, providing powerful fixed-point and floating-point arithmetic capabilities, At the same time the chip internal integration of multicore Navigator, RapidIO, Gigabit Ethernet and EDMA peripherals, due to the chip processing power, peripheral features rich, and on-chip integration of a large number of hardware accelerators, such as packet Accelerator, Multicore Navigator, etc., can be widely used in communications, radar, sonar, fire control, electronic warfare and other fields.  From the present situation, due to the above outstanding characteristics of C6678, based on tms320c6678 hardware and software platform, in the next 5-10 years, will be the signal processing platform mainstream. The following figure shows the C6678 internal structure diagram

The tms320c6678 has 8 c66x cores with a typical speed of 1GHz, with each core configured as: 32KB Level 1 Data SRAM, which operates at the same speed as the DSP core and can be used as normal data memory or data cache;  32KB level 1 Program SRAM, which operates at the same speed as the DSP core, can be used as a normal program memory or program CACHE;512KB LL2 SRAM, which runs at a speed of half the DSP core and can be used as a normal memory or cache, which can store data or store programs All DSP cores share 4MB SL2 SRAM, which runs at half the speed of the DSP core, which can store data or store programs. A 64-bit 1333MTS DDR3 SDRAM interface can support 8GB external expansion memory. The C6678 integrates a 64-bit 1333MTS DDR3 SDRAM interface to support 8GB external expansion memory, which can store data or store programs. Its bus width can also be configured as either the bits or the bits.   Memory access performance is critical to the efficiency of software operation on the DSP. On the C6678 DSP, all the main modules, including multiple DSP cores and multiple DMA, all have access to all the memory.   Each DSP core can perform up to $ bits of load or store operation per clock cycle. At 1GHz clock frequency, the DSP core accesses l1d SRAM bandwidth can reach 16gb/s. When accessing level two (L2) memory or external memory, access performance depends primarily on how and when the cache is accessed.   Each DSP core has an internal DMA (IDMA), which supports transmission up to 8gb/sec at a clock frequency of 1GHz. However, IDMA can only access L1 and LL2 and configuration registers, which cannot access external storage. The internal bus switching network of the DSP, TeraNet, provides the interconnection between the c66x core (including its local memory), the external memory, the EDMA controller, and the on-chip peripherals. A total of 10 EDMA transfer controllers can be configured to perform data transfer between any memory at the same time. Inside the chip there are two main teranet modules, one to connect each endpoint with the X-bit bus, the speed is 1/3 of the DSP core frequency, theoretically, each port on the 1GHZ device supports 5.333gb/-second bandwidth; another teranet internal bus switching network with a bit Bus connection per endpoint, speed is DS1/2 of the P-core frequency, theoretically, each port on a 1GHz device supports 16gb/-second bandwidth.   Summary as shown in the figure below