Introduction to the pin in Altera FPGA

The first step must be the pin planner, which is the view of the four generations of black gold ep4ce15f17c8.

The first is to find that their pin has different color areas, which correspond to different banks respectively. Some designs require that the pin be in the same bank (first, this conjecture is followed by verification ), what does different circles and triangles mean? View --> pin legend

In the figure, the pin of several brown backgrounds is used. If you place the cursor on the pin, the pin name is automatically displayed.

Next is the all pin List window.

In this window, a series of information such as pin position, voltage, and current can be specified. Each bank has only one voltage, so how much voltage is specified, and the current must be output so much? Subsequent discussions

Careful friends will find out how SDA does not have a bank. I checked it and found that my TCL does not have any constraints on SDA, Q made a random distribution for this pin-this is a USB data signal line.

 

A friend on the Internet briefly explained: If I/O standard sets 2.5 V, but its vref is connected to 1.8v, then I/O cannot beat 2.5 V.

The larger the current strength, the better. However, the dynamic I/O capability may cause the dynamic SSN and overshooting issue. However, weak current strength may trigger multiple FPGA mutual attacks, or when multiple fan-out instances are added to the external server

 

 

Introduction to the pin in Altera FPGA