Introduction to the timer module TT of or1200 Processor

The following is an excerpt from the book "Step by Step surprise core-software core processor internal design analysis ".

 

16.2.1 TT Introduction

The timer module (tick Timer: TT) is generally used for operating system process scheduling, user program timing reference, and so on. Within TT, the clock cycle is counted. When the counter value reaches a preset value, an interruption occurs and the processor is notified to process the data. The main body of the implementation is two special registers: the timer unit counting register ttcr and the timer unit mode register ttmr. Through the different configurations of the two SPRS, different working modes are implemented, and timing interruption. Ttcr and ttmr are 10th special registers, as shown in Table 16.4. The formats of ttcr and ttmr are shown in Table 16.5 and 16.6 respectively.

The meanings of each flag in ttmr are as follows:

• TP: the preset timer period in the range of 0x0-0xfffffff
• IP: 1 indicates that a timer is interrupted and waiting for processing.
• IE: 1 indicates that the timer is allowed to interrupt. Otherwise, the timer will not interrupt.
• M: timer Working Mode

The value of ttmr [m] determines the timer working mode. There are four working modes. The timer working process in each mode is as follows:

(1) Auto-Restart Mode

When ttmr [m] is equal to 2'b01, TT works in auto restart mode. In this mode, when the value of ttcr [27:0] is equal to the value of ttmr [TP, the ttcr is cleared and the timer continues. If ttmr [ie] is 1, the timer is declared interrupted.

(2) One-shot mode

When ttmr [m] is equal to 2'b10, TT works in a timing mode. In this mode, when the value of ttcr [27:0] is equal to the value of ttmr [TP, the timer is stopped. If ttmr [ie] is 1, the timer is declared interrupted. After the ttcr is changed, you can continue timing.

(3) continuous Timing Mode

When ttmr [m] is equal to 2'b11, TT works in the continuous Timing mode. In this mode, when the value of ttcr [27:0] is equal to the value of ttmr [TP, the timer continues, that is, the value of ttcr continues to accumulate. If ttmr [ie] is 1, the timer is declared interrupted.

(4) Stop Mode

When ttmr [m] is equal to 2' B00, TT stops working.

In the above modes, the actual declared timer interrupt is to set the value of ttmr [IP] to 1. After the processor responds to the timer interrupt, it will enter the timer interrupt processing routine, however, ttmr [IP] will not be automatically cleared. You must use the program to write 0 to ttmr [IP.

16.2.2 external connection relationships and macro definitions of TT

As shown in Figure 16.2 of the external connection relationship of the timer module TT in or1200, the direction of the arrow indicates whether the signal is input or output. Interfaces starting with spr_xxx are all signals related to reading and writing of special registers, which also have a clear meaning. In addition, Intr 1 indicates that the timer is interrupted and the signal is output to the interface sig_tick of the CPU module.

The macros related to timers in or1200 are defined as follows:

Or1200_defines.v 'define or1200_tt_implemented // whether to implement the TT module, the TT module is an optional module 'fine or1200_tt_ofs_ttmr 1 'D0 // ttmr, The ttcr register index in the 10th group of special registers 'fine or1200_tt_ofs_ttcr 1 '1' define limit 0' define or1200_tt_ttmr // required define this macro to use the ttmr register 'define or1200_tt_ttcr // you need to define this macro to use the ttcr register 'define register 27:0 // The offset of each flag position in ttmr 'define or1200_tt_ttmr_ip 28' define limit 29 'define or1200_tt_ttmr_m 31: 30 'define or1200_tt_readregs // with this macro definition identifier, you can read the ttmr and ttcr special registers in TT.

 

16.2.3 TT code analysis

The TT code is mainly used to configure different timer working modes, change ttcr in various working modes, and control the generation of timer interruption. The code analysis is as follows (for ease of understanding, I changed the code order ):

Or1__tt.vmodule or1__tt (// RISC internal interfaceclk, RST, du_stall, spr_cs, spr_write, spr_addr, spr_dat_ I, spr_dat_o, Intr );...... 'Ifdef or1200_tt_implemented' ifdef or1200_tt_ttmrreg [31: 0] ttmr; // ttmr register 'elsewire [31: 0] ttmr; 'endif 'ifdef or1200_tt_ttcrreg [31: 0] ttcr; // ttcr register 'elsewire [31: 0] ttcr; 'endif ...... // If spr_cs is 1, the command l is determined based on the priority bit of spr_addr. mfspr/L. the mtspr access target is // ttmr or ttcr, and ttmr_sel is 1, indicating that the access target is ttmr; ttcr_sel is 1, indicates that the access target is ttcrassign ttmr_sel = (spr_cs & (spr_addr ['or1200 _ ttofs_bits] = 'or1200 _ tt_ofs_ttmr ))? 1 'b1: 1' B0; assign ttcr_sel = (spr_cs & (spr_addr ['or1200 _ ttofs_bits] = 'or1200 _ tt_ofs_ttcr ))? 1 'b1: 1' B0; // when ttmr [TP] is equal to ttcr [27:0, match is equal to 1 assign match = (ttmr ['or1200 _ tt_ttmr_tp] = ttcr [27:0])? 1 'b1: 1' B0; // when working in auto-retart mode and ttmr [TP] is equal to ttcr [27:0, the restart is set to 1 assign restart = match & (ttmr ['or1200 _ tt_ttmr_m] = 2 'b01); // There are three cases where stop is 1: (1) when working in one-shot mode and ttmr [TP] is equal to ttcr [27:0], // The timer is stopped and Set stop to 1; (2) when ttmr [m] is set to 2' B00, the timer does not work, and stop is 1; // (3) the timer is set to stop the External Interrupt unit, at this time, du_stall is 1 assign stop = match & (ttmr ['or1200 _ tt_ttmr_m] = 2 'b10) | (ttmr ['or1200 _ tt_ttmr_m] = 2 'b00) | du_stall; 'ifdef or1200_tt_ttmralways @ (Posedge CLK or 'or1200 _ rst_event RST) if (RST = 'or1200 _ rst_value) ttmr <= 32 'b0; else if (ttmr_sel & spr_write) ttmr <= spr_dat_ I; // If ttmr_sel is 1 and spr_write is 1, it indicates to write ttmr else if (ttmr ['or1200 _ tt_ttmr_ie]) // If ttmr [ie] is 1, it indicates to interrupt enabling, when match is equal to 1, // ttmr [IP] is set to 1, ttmr [IP] values are not automatically cleared. ttmr ['or1200 _ tt_ttmr_ip] <= ttmr ['or1200 _ tt_ttmr_ip] | (match & ttmr ['or1200 _ tt_ttmr_ie]); 'else assign ttmr = {2 'b11, 30' B0 }; // If the ttmr register is not set, the value of the variable ttmr is 'endif // from Figure 16.2, we can see that intr is connected to the input sig_tick interface of the CPU, the intr value is the value of ttmr [IP], indicating whether a timer interruption occurs assign intr = ttmr ['or1200 _ tt_ttmr_ip]; 'ifdef or1200_tt_ttcralways @ (posedge CLK or 'or1200 _ rst_event RST) if (RST = 'or1200 _ rst_value) ttcr <= 32' B0; else if (restart) // when the operation is in auto-Restart mode and ttmr [TP] is equal to ttcr [27:0] // the restart is set to 1, and ttcr is cleared at this time, re-start counting ttcr <= 32 'b0; else if (ttcr_sel & spr_write) // ttcr_sel is 1, and spr_write is 1, indicating to write ttcr register ttcr <= spr_dat_ I; else if (! Stop) // As long as stop is not 1, the value of ttcr in each clock cycle is increased by 1 ttcr <= ttcr + 32'd1; 'elseassign ttcr = 32' B0; // If the ttcr register is not set, the ttcr value is 'endifalways @ (spr_addr or ttmr or ttcr) Case (spr_addr ['or1200 _ ttofs_bits]). // Synopsys parallel_case 'or1200 _ tt_ofs_ttmr: spr_dat_o = ttmr; // read ttmrdefault: spr_dat_o = ttcr; // read ttcrendcase 'else // if no TT module is configured, Intr is always 0, and assign intr = 1' B0; assign spr_dat_o = 32' B0; 'endifendmodule