IO timing optimization issues with Altera FPGA

The structure of an IO in Chip planner is shown

The left side is the output section to the right of the input section, but will notice two structure: 1, register, 2,delay module

Here's my guess: These two structures are designed for timing optimization and are mentioned in Altera's timing optimization documentation for the fast input and output registers in the Io cell.

If you have the correct timing constraints, the Quartus software can automatically determine whether the register is placed in the core or IO cell, but can also be set manually, by selecting the pin set in the assignment editor to set manually, if it is input register, put to IO Cell can reduce TSU, if it is output register can reduce TCO,

About programmable delay, there is a passage on the official document

Can be seen, the official is not recommended to adjust programmable delay, after the completion of the compilation to see the timing does not meet the requirements of the situation and then modify programmable delay,

And I found the following form in Device Handbook.

You can adjust the delay so much. The adjustment method is also adjusted in the assignment editor.

IO timing optimization issues with Altera FPGA