Java underlying implementation-CPU terminology

1. Memory barriers is a set of processor directives that enable sequential limits on memory operations

2. The minimum storage unit that can be allocated in the buffer line (cache lines) CPU cache. Processor fills in cache lines

The entire cache line is loaded, and the modern CPU needs to execute hundreds of CPU instructions

3. Atomic operations (atomic operations) non-disruptive one or a series of operations

4. Cache line Fill (cached lines fill) when the processor recognizes that the read from memory operand is cacheable, the processor

Fill in the entire cache line to the appropriate cache (L1,L2,L3 or all)

5. Cache hit if the memory location of the cache row population operation is still the next time the processor accesses the

Address, the processor reads the operand from the cache instead of reading from memory

6. Write hits (write hit) when the processor writes the operand back to the area of a memory cache, it first checks the

The memory address of the cache exists in the row, and if there is a valid cache line, the processor writes the operand back to the cache,

Instead of writing back to memory, this operation is called a write hit.

7. Write missing (write misses the cache) a valid buffer line is written to a memory area that does not exist

8. Compare and swap (compare and swap) CAS operations need to enter two values, an old value (the value before the expected operation)

And a new value, the old value is not changed during operation, and if it has not changed, it is changed to the new value.

Then do not exchange

The 9.CPU pipelining (CPU Pipeline) CPU pipelining works just like an assembly line in industrial production, in the CPU by 5-6

The different functions of the circuit unit constitute an instruction processing line, and then a X86 instruction is divided into 5-6 steps after the circuit units are executed separately,

This enables a CPU clock cycle to complete an instruction, thus increasing the CPU's computational speed

10. Memory Order conflict (violation) memory order conflicts are usually caused by false sharing, which means that multiple CPUs are simultaneously modified

A different part of a cache line causes one of the CPUs to be invalid, and when this memory sequence conflict occurs, the CPU must empty the pipeline

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Java underlying implementation-CPU terminology