Jlink using the tutorials and the differences with JTAG

It's not easy for a novice.

and learning from the beginning is a very good thing.

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To debug arm, JTAG is one of the following arm 's debug interface protocols. When simulation, IAR, KEIL, ads, etc. have a common debugging interface, RDI is one of them, then how do we complete the Rdi-->arm Debug Protocol (JTAG) conversion? There are two ways to do this:

1. Write a service program on the computer, parse the RDI command in the IAR, Keil, and ads into the relevant JTAG protocol, and then pass through a physical conversion interface (Note that this conversion is just a conversion on the electrical physical layer, just like the role of RS232) to send your target board. That's the way H-jtag is. H-jtag's hardware is just a physical level conversion interface, so it's simple. And the computer in the H-jtag software is said before the service program, responsible for the conversion of the Protocol.

2. Make a board, use this board to receive directly from the IAR, Keil and ads and other software debugging commands, the Board do Rdi->jtag protocol conversion. Then communicate with the target board, which is how Jlink works.

From the above can be seen H-jtag because it is the software for protocol conversion, so the speed is slow, but the hardware is simple. And the second method of Jlink generally with a strong CPU, for hardware protocol conversion, the hardware complex, but fast.

Fundamentals of Jtag

JTAG (Jointtestactiongroup, Joint Test Action Group) is an international Standard test protocol (IEEE1149.1 compatible). The standard JTAG interface is a 4-wire--tms, TCK, TDI, TDO, mode selection, clock, data input, and data output lines, respectively.

There are two main functions of JTAG, or there are two main types of JTAG:

1) A class for testing the electrical characteristics of the chip, detection chip whether there is a problem;

2) Another class for debug, all kinds of chips and their peripherals to debug; A CPU with a Jtagdebug interface module, as long as the clock is normal, can access the internal registers of the CPU via the JTAG interface, the devices hanging on the CPU bus, and the registers of the built-in modules. This article is mainly about the debug function.

JTAG Principle Analysis

To put it simply, JTAG works by defining a tap (testaccessport, test access port) inside the device and testing and debugging the internal node with a dedicated JTAG test tool. First, the basic concepts and contents of boundary scan and tap are introduced.

Boundary scan

The basic idea of boundary scan (Boundary-scan) technology is to add a shift register unit to the input/output pin near the chip, which is the Boundary Scan Register (boundary-scanregister).

When the chip is in the debug state, the Boundary scan register can isolate the chip from the external input/output. Through the Boundary Scan Register unit, can realize to the chip input/output signal observation and the control. For the input pin of the chip, the signal (data) can be loaded into the pin by the boundary Scan Register unit connected with it, and the output signal on the pin can also be "captured" by the boundary scan register connected with it for the output pin of the chip. In the normal running state, the boundary scan register is transparent to the chip, so the normal operation will not be affected. In this way, the boundary Scan register provides a convenient way to observe and control the chips needed for debugging. In addition, the boundary Scan (shift) register units on the chip input/output pins can be connected to each other, forming a boundary scan chain (Boundary-scanchain) around the chip. The boundary scan chain can be serially input and output, through the corresponding clock signal and control signal, it can easily observe and control the chip in the debugging state.

Test Access Port Tap

Tap (Testaccessport) is a universal port that provides access to all data registers (DR) and instruction registers (IR) provided by the chip via tap. The control of the entire tap is done through the TAP controller (Tapcontroller). The following first introduces several interface signals of tap and their functions. Among them, the first 4 signals in the IEEE1149.1 standard is mandatory.

TCK: A clock signal that provides a separate, basic clock signal for the operation of the tap.

TMS: Mode selection signal for controlling the conversion of a tap state machine.

TDI: Data input signal.

TDO: Data output signal.

TRST: Reset signal, can be used to reset the Tapcontroller (initialization). This signal interface is not mandatory in the IEEE1149.1 standard because the Tapcontroller can also be reset via TMS.

STCK: Clock return signal, non-mandatory in the IEEE1149.1 standard.

Simply put, the PC's debug of the target board is to access the relevant data register (DR) and instruction Register (IR) via the tap interface.

After the system is power up, Tapcontroller first enters the Test-logicreset state, then enters Run-test/idle, Selcct-dr-scan, Select-ir-scan, Capture-ir, Shift-IR , Exitl-ir, Update-ir status, and finally back to Run-tcst/idle state. In this process, the transfer of the state is driven by the TCK signal (rising edge), and the status of the tap is selected for conversion through the TMS signal. Wherein, in the Capture-ir state, a specific logic sequence is loaded into the instruction register, in the Shift-ir state, a specific instruction can be sent to the instruction register, in Update-ir state, the instructions just entered into the instruction register will be used to update the instruction register. Finally, the system returns to the Run-test/idle state, and the command takes effect to complete the access to the instruction register. When the system returns to the Run-test/idle state, the data register is selected according to the contents of the preceding instruction register, and the operation of the database is started. Its basic principle and instruction register access exactly the same, in order Seiect-dr-scan, CAPTURE-DR, shift-d, exitl a DR, UPDATE-DR, and finally back to the Run-tcst/idle state. With TDL and TDO, new data can be loaded into the data register. After a period of time, the data in the data registers can be captured, the data of the chip pin connected to each register unit of the data register is updated, and the data registers are accessed.

Currently, the JTAG interface on the market is available in both 14-pin and 20-pin types. Among them, the 20-pin mainstream standard, but there are a few target boards with 14-pin. After a simple signal conversion, they can be generalized.

Jlink using the tutorials and the differences with JTAG