Know (ii)--I2C bus SDA\SCL and start termination conditions

I²C transmits data between devices connected to the bus using only two lines (SDA and SCL). Each device is identified by a unique address (whether it is a microprocessor, LCD driver, memory, or keyboard interface) and can be used as a transmitter or receiver depending on the function of the device. The LCD driver may be just a receiver, and the memory can send and receive data. In addition to transmitters and receivers, the device can be used as a host or slave when transmitting data. The host is the device that initializes the data transfer and generates the clock signal, at which point any addressed device is a slave.

The I²c bus is a multi-host bus. means that you can connect multiple devices that can control the bus to the bus. The host is typically a microcontroller, and we can consider the following two cases of data transmission between the microprocessors connected to the bus.


This example highlights the relationship between the master-slave and receiver-sender in the I²C bus. Note that these relationships are not fixed and depend only on the direction of the current data transfer. The process of data transfer is as follows:
1. Assume that microcontroller a sends data to microcontroller B
Microcontroller A (host) addressing microcontroller B (slave)
Microcontroller A (host-transmitter) sends data to microcontroller B (slave-receiver)
Microcontroller a ends data transfer
2. Assume that microcontroller a receives data from microcontroller B
Microcontroller A (host) addressing microcontroller B (slave)
Microcontroller A (host-receiver) receives data from microcontroller B (slave-transmitter)
Microcontroller a ends data transfer
Even in this case, the host (microcontroller a) produces timing and terminates the transmission.
When multiple microcontrollers are connected to the I²C bus, it means that multiple hosts may attempt to initialize the data transfer. In order to avoid the confusion caused by this, an arbitration mechanism was designed. It relies on the line and logic to connect all I²c interface to the I²c bus.
If more than one host attempts to send information to the bus, in the case of other "0", the first generation of "1" of the main opportunity to throw a quorum. The clock signal at the time of the arbitration is the synchronization of the clock generated by the line and the host connected to the SCL line.
The host devices on the I²C bus are usually responsible for generating clocks, and each host generates its own clock signal when transmitting data. The bus clock of the host is changed only at low speeds when the clock line is controlled from the device or when the quorum occurs.
The following table summarizes some of the configuration options in the I²c bus:

[1] This is also referred to as the slave machine
[2] The clock stretching is the characteristic of the partial slave. If the clock is stretched in the system without a slave (the SCL is pulled down), the host must design the handler
[3] ' Bit banging ' (software emulation) Multiple host systems should consider the start byte

SDA and SCL signals
Both SDA and SCL are bidirectional lines that are connected to a forward voltage via a current source or pull-up resistor. (see figure below) when the bus is idle, both lines are high. The output stage of the device connected to the bus must be an OD (open-drain) or OC (open collector) gate to perform the line and function. In standard mode, the I²C bus transmits data to 100kb/s speed, while in fast mode it achieves 400kb/ s speed, fast plus mode is the speed of the 1mb/s, tells the mode is 3.4mb/s speed. The capacitance of the bus limits the number of interfaces connected to the bus.
For a single host application, if no device on the bus can pull down the clock then the host's SCL output should be a push-pull (push-pull) drive design.


Logic level for SDA and SCL
Due to the various process devices (CMOS NMOS bipolar) can be connected to the I²C bus, low and high levels are not fixed but depend on the level of the corresponding VDD.

Data validity
The data on the SDA line must be stable at the time of the clock. Only when the clock signal on the SCL line is low can the data line change the high and low state. Each data bit transfer requires a clock generation.


Start and end conditions
All transmissions begin with a start (S) and a Stop (P) terminates.
The start condition is when the SCL is high and the SDA is high to low
The stop condition is an SCL high when the SDA is low to high


The start condition and the termination condition are always generated by the host. The bus is busy after the start condition. The bus is idle at a fixed time after the termination condition. If there is no termination condition, but a repeating start condition (SR), the bus is still busy. In this case, S and Sr are functionally identical .
If the device that is connected to the bus contains the necessary interface hardware then it is easy to detect the start condition and termination condition. But there is no such interface for the microcontroller to sample at least two SDA lines per clock cycle to identify any level changes.