Knowledge of ARM bus

　　

About Amba

With the development of deep submicron technology, the scale of IC chips is becoming larger and bigger. The digital IC has been developed from the design method based on sequential drive to the design method based on IP multiplexing, and has been widely used in SOC design. In the design of SOC based on IP multiplexing, the design of on-chip bus is the most important problem. For this reason, there are many on-chip bus standards in the industry. The Amba on-chip bus, introduced by arm, is favored by many IP developers and SOC system integrators, and has become a popular industry standard on-chip structure. The AMBA specification mainly includes the AHB (Advanced Performance Bus) system bus and the APB (Advanced peripheral bus) peripheral bus.
Amba on-chip bus
The AMBA 2.0 specification consists of four sections: AHB, ASB, APB, and test methodology. The interconnection of the AHB is based on the traditional shared bus with the main module and from the module, and the interface is separated from the interconnection function, which is of great significance to interconnect between the modules on the chip. Amba is not only a kind of bus, but also a interconnection system with interface module. The more important AHB and APB buses are briefly described below.

Amba-based on-chip systems

A typical AMBA bus-based system is shown in block Diagram 3.

Most modules that hang on the bus (including processors) are simply functional modules of a single attribute: The main module or the slave module. The main module is the module that sends the read and write operation from the module, such as CPU,DSP, etc., from the module is the module that accepts the command and reacts, such as the RAM,AHB/APB Bridge on the chip. In addition, some modules have two properties at the same time, such as direct memory access (DMA) is programmed to be from the module, but must be the main module when the system reads the transmitted data. If more than one master module exists on the bus, the arbiter is required to determine how to control access to the bus from various master modules. Although the arbitration specification is part of the AMBA Bus specification, the specific algorithm used is determined by the RTL design engineer, of which two of the most commonly used algorithms are fixed-priority algorithms and cyclic algorithms. There can be up to 16 main modules and any number of slave modules on the AHB bus, and if the number of master modules is greater than 16, a further layer is required (see the Multi-layer AHB specification, introduced by arm). The APB Bridge is both the only main module on the APB Bus and the slave module on the AHB system bus. Its main function is to latch the address, data, and control signals from the AHB system bus and provide a two-level decoding to generate a selection signal for the APB peripherals, thus enabling the conversion of the AHB protocol to the APB protocol.

AHB Introduction
AHB is mainly used for the connection between high-performance modules (such as CPU, DMA, DSP, etc.), as the SOC on-chip system bus, which includes the following features: Single clock edge operation, non-tri-State Implementation mode, support burst transmission, support segmented transmission, support multiple host controllers, configurable 32-bit ~ 128-bit bus width, byte, half byte, and word transmission support. The AHB system consists of a master module, a module and an infrastructure (Infrastructure) 3 part, the transmission of the entire AHB bus is issued by the main module, from the module responsible for response. The infrastructure consists of an arbiter (arbiter), a master module, a multiplexer from a module, a multiplexer from a module to a master module, a decoder (decoder), a virtual slave module (dummy Slave), and a virtual Master module (dummy master). Its interconnect structure is shown in 1.

About APB
APB is primarily used for connections between low bandwidth peripheral peripherals, such as UART, 1284, etc., and its bus architecture does not support multiple main modules like AHB, the only main module in the APB is the APB Bridge. Its characteristics include: two clock cycle transmission, no waiting period and response signal, simple control logic, only four control signals. The transmission on the APB can be illustrated by the status diagram shown in 2.

1) The system is initialized to the idle state, there is no transfer operation at this time, and no slave module is selected.
2) When there is a transmission to be carried out, pselx=1,penable=0, the system enters the setup state and only stays in the setup state for a period. When the next rising edge of the PCLK arrives, the system enters the Enable state.
3) When the system enters the Enable state, the PADDR, Psel, pwrite unchanged in the setup state are maintained, and the penable is set to 1. The transfer is also only maintained in the Enable State for a period, after the setup and enable state has been completed. Then, if there is no transmission to proceed, it enters the idle state, and if there is a continuous transmission, it enters the setup state.

The following is the s3c2410 BLOCK DIAGRAM

Knowledge of ARM bus