LAN switch architecture and Performance

The introduction of multi-layer switching architecture effectively increases the speed of LAN and provides an understanding of the queuing model, exchange implementation, and exchange structure of the multi-layer switching architecture, the performance improvement of LAN switches can be realized more deeply.

Queuing Model

The switching structure refers to the "highway" for data from one endpoint to another. queuing is a buffer mechanism used to control congestion. When the switching structure is congested, it will directly affect the performance of the vswitch to a large extent, so it is necessary to carry out congestion management. Congestion management is required when multiple ports compete for the same port and information packets are queued.
Queuing can adopt Dynamic Buffer queuing or fixed buffer queuing, where the length of the buffer during Dynamic Buffer queuing is fixed increment, for example, 64 K Bytes each time), so that the buffer resources can be used more effectively; while the buffer length is fixed when the fixed buffer is sorted, so the buffer usage efficiency is not high, but the cost is lower than the custom controller custom controllers.
Queuing can be performed on the input port of the switching structure, that is, the input queue, or on the output port of the switching structure, that is, the output queue. During the input queue, the information packet is buffered at the entry port. The maximum throughput can be reduced by 60%, but the line is blocked. During the output queue, the buffer is set at the output port, wireless Access is blocked, but buffer overflow occurs during traffic peaks.

Exchange implementation

Exchange implementation is used to describe the location and method of the Exchange decision-making: whether it is local or central, whether it is longest match or accurate match.
The place where the exchange decision is made is the central place, that is, the centralized exchange. Centralized exchange uses a centralized sending table to provide centralized control for exchange and recognition. To achieve fast implementation, the query is completed by ASIC, and the centralized exchange can perform layer-4 or layer-2nd queries.
In distributed switching, the switching decision is made by the port or module locally. the Layer 2 and Layer 2 tables must be synchronized to indicate adding, moving, or modifying.
The exchange implementation can also be divided into traffic-based exchange and forwarding information library-based exchange. Traffic-based switching is a demand-based switching. The entry contains the source address, target address, and/or layer-4 information. The first information packet processed is exchanged by the path processor, the information packages in this stream are switched by the path high-speed cache. The traffic high-speed cache decision is made locally and/or in the center, and all information packages are exchanged at Layer 1.
Based on the forwarding information library, the exchange is based on the topology, And the cache is pre-installed based on the route table rather than the traffic. No process switching is required for the information package to enter the vro. The decision-making can be performed locally or in the center, regardless of the switch structure.
Exchange Structure

The switching structure includes two layers: Bus and shared memory.
When a single bus is used, the FDDI uplink module, the ATM uplink module, the Ethernet Switching module, and the Fast Ethernet Switching Module are connected to a central fabric element, each port must be connected to arbitration. It is easy to broadcast and multi-point broadcast using a single bus, but it is prone to overload.
When a cross-bus structure is used, multiple input buses can be used to establish a vertical and horizontal structure, which generally does not cause blocking. However, it is complicated to broadcast or multi-point broadcast, for example, when forwarding a query table.
The switch has a memory pool). All modules of the switch share the memory pool. Switch Input to memory is managed by ASIC, switch core switching core) performs the query function, breaks down the target address into pointers in memory, and then exchanges information packets. The buffer can be fixed or dynamic. If the architecture is not blocked, the required buffer can be smaller.

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