(LDD) Chapter 1 PCI driver

1. The bus is composed of an electrical interface and a programming interface. Kernel functions used to access peripherals of Peripheral Component Interconnect (PCI, peripheral device interconnection,
Because PCI bus is widely used on desktops and peripherals on larger computers today, and bus is the best supported bus in the kernel, ISA bus is basically
It is a "bare metal" type bus.
2. Three main objectives of pci: To achieve better performance when data is transmitted between the computer and peripherals; to minimize platform independence; to simplify the process of adding and deleting peripherals to the system.
By using a clock frequency higher than ISA, the PCI bus achieves better performance. Its clock frequency is generally 25 m or 33 MHz (the actual frequency is the system clock coefficient)
The latest implementation is 66 MHz or even 133 MHz. A 32-bit data bus that includes 64-bit extensions. Platform independence.
Driver problems: automatic detection of the interface board, PCI devices are non-jumper devices, can be automatically configured in the boot phase. The device driver must be able to access the device.
To complete initialization.
3. Each PCI peripheral is identified by a bus number, a device number, and a function number. Linux supports PCI domains. Each domain supports 256 bus and each bus.
Supports 32 devices. Each device supports 8 features. Each function can be identified by a 16-bit address (or key) at the hardware level. Device Drivers written in Linux
You do not need to process these binary addresses because they use a special data structure (called pci_dev) to access devices.
4. The current workstation is generally configured with at least two PCI buses. inserting multiple buses into a single system can be completed through a bridge. It is used to connect two
The special PCI peripherals of the bus.
The 16-bit hardware address associated with PCI peripherals is often hidden in the struct pci_dev object. The output of lspci and the layout of information in/proc/PCI and/proc/bus/PCI are
This is the case. The PCI domain displays two values (one eight-bit bus number and one eight-bit device and function number), and sometimes three values (bus, Device
And functions), display four values (domain, bus, device and function), All values are usually displayed in hexadecimal notation.
It can be divided into domains (16 bits), bus (8 bits), device (5 bits), and function (3 bits) 0x00a0, indicating. 0
5. Each hardware circuit queries and responds to the following three address spaces: memory location, I/O port, and configuration register. The first two address spaces are all devices on the same PCI bus.
Shared (that is, when the memory is accessed), all devices on the PCI bus view the bus cycle at the same time.
On the other hand, the geographical addressing used by the configuration space is configured to address only one slot at a time, so they do not conflict at all.
For drivers, the memory and I/O areas are accessed in the usual way, namely through INB and readb. On the other hand, configuration transactions are accessed through specific kernel functions.
Configure registers for execution.
6. For interrupt, each PCIe slot has four interrupt pins, one of which can be used by each device, regardless of how these pins connect to the CPU. This
Routing is also the responsibility of the computer platform to implement outside of the PCI bus.
Because PCI specifications require shared upon interruption, any processor with a limited IRQ line can accommodate many PCI interface boards (each with four interrupt pins ).
The I/O space in the PCI bus uses the 32-bit address bus (4G ports), while the memory space can be accessed through 32-bit or 64-bit addresses.
It is generally assumed that the address is unique to the device, but the software may incorrectly configure the two devices to the same address, resulting in the inability to access the two devices.
7. Each memory and I/O address area provided by the interface board can be re-mapped by configuring transactions, that is, the firmware is initialized during system boot.
PCI hardware maps each region to a different address to avoid conflict. The addresses of these mapped regions can be read from the configuration space. Therefore, the Linux driver
The program can access the device without detection. After reading the configuration register, it can safely access its hardware.
8. The configuration register layout is standardized. The four bytes of the configuration space contain a unique feature ID. Therefore, the driver can query the specific ID of the peripherals.
Each device obtains its configurator through geographical addressing. The information in these registers can then be used to perform general I/O addressing.
No additional geographic addressing is required.
9. The main innovation of the PCI interface standard on ISA lies in the configuration space. The PCI driver also needs the ability to access the configuration space to avoid risky detection.
10. The configuration of the PCI device starts at the system boot. When the PCI device is powered on, the hardware remains inactive. In other words, the device can only perform configuration transactions.
Response.
11. By reading and writing the registers in the PCI Controller, the firmware provides access to the address space configured for the device. During system boot, the firmware (or Linux kernel, if
Configuration) execute the configuration transaction on each PCI peripheral to assign a safe location to each address area provided by the PCI peripheral when the driver accesses the device.
Its memory and I/o Region have been mapped to the address space of the processor.
/Proc/bus/PCI/devices/AND/proc/bus/PCI/* view the device list and configuration registers. The former is a device that contains hexadecimal notation, and the latter
Is a number of binary files that report the configuration register snapshot for each device.
12. All PCI devices have at least 256 bytes of address space. The first 64 bytes are standardized, while the rest are device-related. Some PCI configuration registers are required
Some are optional. Each PCI device must contain valid values in a required register, and the content in the optional Register depends on the actual capabilities of the peripherals.
PCI registers are always small. Note that the PCI byte sequence is always small.
13. How the driver queries the device and how to access the configuration space of the device.
Three or five PCI registers are used to indicate a device: vendeorid. DeviceID and class are commonly used three registers. Each PCI manufacturer assigns the correct value to these three registers.
Read-only registers that can be used by drivers to query devices.
Vendorid, a 16-bit register used to identify the hardware manufacturer.
DeviceID, 16 registers, selected by the manufacturer. You do not need to register the device ID.
Class each external device belongs to a class ).
The PCI driver can use different identifiers to tell the kernel what devices are supported. The struct pci_device_id struct is used to define the driver support.
List of different types of PCI devices.
14. Use two secondary macros to initialize the struct pci_device_id struct:
Pci_device (vendor, device). This macro sets the subvendor and subdevice fields to pci_any_id.
Pci_device_class (device_class, device_class_mask );
15. The pci_device_id struct needs to be exported to the user space, so that the hot plug-in and module loading systems can know what modules are for what hardware devices. Macro module_device_table
Complete this task
Module_device_table (PCI, i810_ids );
The depmod program searches all modules for the symbol _ mod_pci_device_table.
16. The main struct that all PCI drivers must create is the struct pci_driver struct. This struct is composed of many functions and variables and is directed to the PCI core.
Describes the PCI driver.
Const char * Name; name of the driver, which is generally the same as the name of the PCI driver module and must be unique.
Const struct pci_device_id * id_table;
INT (* probe) (struct pci_dev * Dev, const struct pci_device_id * ID );
This function is called when the PCI core is used to determine a struct pci_dev to be controlled. The PCI core is used to determine the struct pci_device_id pointer.
It is also passed to this function. If an error occurs, it should return a negative error value.
Void (* remove) (struct pci_dev * Dev) points to a remove function pointer.
INT (* suspend) (struct pci_dev * Dev, u32 state) points to a suspended function pointer.
INT (* resume) (struct pci_dev * Dev) points to a recovery function pointer.
To create a correct struct pci_driver structure, you only need to initialize four fields:
Static struct pci_driver = {
. Name = "pci_skel ",
. Id_table = IDs,
. Probe = probe,
. Remove = remove,
};
17. The old-fashioned manual search system for the list of PCI devices calls a function that can find a specific PCI device.
Struct pci_dev * pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev * From );
Before the driver can access any device resource of the PCI device, the driver must call the pci_enable_device function.
Int pci_enable_device (struct pci_dev * Dev );
18. Memory, port, and configuration are crucial for driver access to the configuration space, because it is used to find out what the device maps to memory and I/O space.
Location.
Because the processor does not have any direct access to the configuration space, computer vendors must provide a way. To access the configuration space, the CPU must read/write
The registers of the PCI Controller, but the specific implementation depends on the computer vendor.
19. Linux provides a standard interface for accessing the configuration space,
Int pci_read_config_byte (struct pci_dev * Dev, int where, u8 * val)
Int pci_read_config_word (struct pci_dev * Dev, int where, 2010* Val)
Int pci_read_config_dword (struct pci_dev * Dev, int where, u32 * val)
Read one or two four bytes from the device configuration space marked by Dev. The where parameter calculates the byte offset from the starting position of the configuration space and
The obtained value is returned through the Val pointer. the return value of the function itself is an error code.
Int pci_write_config_byte (struct pci_dev * Dev, int where, u8 * val)
Int pci_write_config_word (struct pci_dev * Dev, int where, 2010* Val)
Int pci_write_config_dword (struct pci_dev * Dev, int where, u32 * val)
The value to be written is passed through Val.
Replace the following function when the driver cannot access struct pci_dev:
Int pci_bus_read_config_byte (struct pci_bus * bus, unsigned int devfn );
The pci_bus * And devfn variables need to be used, instead of struct pci_dev;
20. a pci device can implement up to 6 I/O address areas. Each area can be memory or I/O address. Most devices implement I/O registers in the memory area. Because this usually
Is a more sensible method. When I/O registers should not be cached by the CPU, because each access may have a marginal effect, the I/O registers are implemented as the PCI devices in the memory area
Memory is a prefetch identifier, and non-prefetch memory access cannot be optimized.
An Interface Board reports the size and current position of its region by configuring registers. The PCI-defined I/O space is a 32-bit address space, so the memory and I/O use the same
The configuration interface makes sense. If the device is 64-bit, two consecutive pci_base_addresses are used in each region to declare the 64-bit memory space area.
21. In the kernel, the I/O Region of the PCI device has been integrated into the general resource manager, so we do not need to know where the memory or I/O space is mapped.
22. By using the pci_resource _ series functions, the device driver can completely ignore the underlying PCI registers because the system has already built these registers.
Resource Information.
23. In the Linux boot phase, the computer firmware has assigned a unique interrupt number to the device, and the driver only needs to use this interrupt number. Interrupt number Storage
In the configuration register 60 (pci_interrupt_line), this register is a byte width.
If the device does not support interruption, the value of register 61 (pci_interrupt_pin) is 0, otherwise it is not 0.
24. The PCI connector has four interrupt pins, which can be any or all of the peripherals. Each pin is independently connected to the Controller of the motherboard and is used by the read-only configuration pin in the pci_interrupt_pin
Tell the computer the pin actually used
The pci_interrupt_line register is read/write. In the computer boot phase, the firmware scans its PCI device and connects to the pci slot based on the interrupt pin.
To set the device register. For the corresponding driver, pci_interrupt_line is read-only.
25. In PCI management, the only hardware-dependent operating room reads and writes configuration registers, because any other work in the PCI world is directly read and
Write I/O and memory address space, which are directly controlled by the CPU.
26. The biggest disadvantage of ISA is that it is closely tied to the PC architecture. The lack of geographic addressing leads to a long "unplugging-re-jumper" process when new devices are added.
Insert-test period.
An ISA device can be equipped with I/O Ports, memory areas, and disconnection.
The unique facility is the I/O port register and the IRQ line.
27. External Bus: USB, these bus are neither fully functional interface bus nor dumb communication channel, hardware controller drivers, drivers for customer devices.