Learning Based on lpc2103: timer 0 and timer 1

The two days to learn the timer of the lpc2103. I started to look at the previous register introduction. I felt dizzy and I was confused later. However, when I see the following operations using the image to describe the timer-related registers, it will be clear. After you know the application, you can see the principle again.

 

Why are these two timers put together, because they are both 32-bit timers, which are the same except for the peripheral base address.

Let's talk about the features of these two timers.

1. Two 32-bit Timer/counter each contain a programmable 32-bit pre-divider;

2. counter or timer operations;

3. The timer 0 has three channels, and the timer 1 has four capture channels. When the input signal changes, the instantaneous timer value can be obtained, or the capture event can be interrupted;

4. Each timer has four 32-bit matching registers. The following three actions are taken during the matching:

When matching, the timer continues to work. You can choose to generate an interrupt.

When matching, the timer stops working and you can choose to interrupt.

Reset the timer when matching. You can choose to interrupt the timer.

5. There are 3 timer 0 and 4 timer 1 correspond to the external output of the matching register. The output of matching is as follows:

Set to low when matching

Set to high when matching

Flip When matching

No action during Matching

6. For each timer, up to four matching registers can be configured as PWM, and up to three matching outputs can be used as PWM output controlled along a single side.

 

If it is followed by a large push register, it is certainly sleepy. In the beginning, I started to look at the various registers from the beginning. However, in another way, starting from the timer application, let's take a closer look at the timer registers, and then we will suddenly become quite open.

 

There are three timer applications. One is simply used as a timer, and the other is used as a comparison matching. Third, the timer is used as the capture function.

 

First look at the module diagram of the register when the timer is used as the timer function

The counter frequency of the 1.32-bit timer TC is obtained by fpclk through the pre-division counter.

2. start/stop of the timer, and reset the count with the control of the CTL.

3. It should be noted that the timer overflow will not interrupt, And the timer interruption is triggered by the capture event or matching event, so the last line is the dotted line.

 

Let's look at the register block diagram when the timer is used for comparison and matching.

1. The comparison and matching functions of the timer are controlled by the MCR register.

2. mr0 ~ 3 stores the comparison values of the four matching comparison channels.

3. When a matching occurs, interrupt or reset TC according to the MCR setting method.

4. When matching occurs, EMR controls the output of the matching Pin-high, low, and pin-level flip.

 

The block diagram of the registers when the timer is used as the capture function.

1. The timer capture function is controlled by the register Cr.

2. The capture event can be set to a rising edge trigger through the CR register. The Descent edge trigger and bilateral trigger

3. Using the CR register, you can set whether an interruption occurs when a capture event occurs.

4. Cr0 ~ 3 is a four-path capture register, saving the corresponding capture value

 

Seeing the three functions of the timer above, the operation method is naturally clear:

1. Calculate the timer clock frequency, and set the PR register for frequency division.

2. If the matching function is used, you need to configure the initial value of the matching Channel and its working mode. If the capture function is used, you need to set the register related to the capture function.

3. If you want to use the timer to interrupt, you need to set the vic to enable interruption. ,

4. Finally, set the CRTs and start the timer.

The timer counting clock frequency is as follows:

Counting clock frequency = fpclk/(n + 1)

N is the value of PR.

 

I know a rough idea and then look at the specific register. I think this is better.

First, register summary to see the total number of registers for timer 0 and timer 1:

The following describes the Register categories. Let's talk about the basic registers:

1. Interrupt mark register (t0ir, t1ir)

Contains four identifier bits used to match the interrupt, and four identifier bits used to capture the interrupt. The specific description is as follows: if an interrupt occurs, the corresponding register location is 1; otherwise, it is 0. If 1 is written to the corresponding flag, the interrupt flag is cleared. If 0 is written, the result is invalid.

2. Timer control registers (t0cr, t1cr)

This register is used to control the operation of the timer counter.

3. Timer counters (t0tc, t1tc)

When the Pre-division counter reaches the upper limit of the counter, the 32-bit timer counter TC plus 1. As shown in, if TC is not reset until it reaches the upper limit of the count, it will count until 0xffffffff and then flip to 0x00000000. This event will not be interrupted. If necessary, use the matching register to detect overflow.

4. Pre-division register (t0pr, t1pr)

The 32-bit pre-division Register specifies the maximum value of the pre-division counter.

5. Pre-division counter registers (t0pc and t1pc)

The pre-division counter uses a constant to control the division of pclk, which can control the relationship between timer resolution and timer overflow. The pre-division counter adds 1 to each pclk period. When the value saved in the pre-division register is reached, the timer counter adds 1 and the pre-division counter resets in the next pclk period. When Pr = 0,

The timer counter adds 1 to each pclk. When PR is set to 1, the timer counter adds 1 to every two pclk cycles, as shown in.

 

The second part of the register is described below, which matches the function register group.

The matching function register group includes the matching register, matching control register, and external matching register. The matching register is used to store the matching value of the timer. When a matching event occurs, the matching control register is used to set the timer. The external matching register is used to set the action of matching the output pin.

1. Matching register (mr0 ~ MR3)

The matching register is continuously compared with the timer Count value (TC). When the two values are equal, an interrupt is automatically triggered, and the timer counter or stop Counter is reset. The executed action is controlled by the MCR register.

2. Matching control registers (t0mcr, t1mcr)

Controls the operations performed by the timer when matching occurs.

3. External matching register (t0emr, t1emr)

The external matching register provides the external matching Pin matn.0 ~ Matn.3 (N is 0 or 1. When the matching output is PWM output, the function of the external matching register is determined by PWM.

 

The following describes the register group of the capture function.

It includes capture registers and capture control registers. The capture control register is used to set the capture signal. When a capture event occurs, the Count value of the timer is saved to the capture register.

1. Capture register (Cr0 ~ (Optional)

Each capture register is associated with a device pin. When a specific event occurs on the pin, you can load the timer Count value into this register, the setting of the capture control register determines whether the capture function is enabled and whether the capture event occurs on the rising, descending, or bilateral edges of the pin.

2. capture control register

Features:

Set the location where the event is captured, the rising edge, the falling edge, or the rising edge + the falling edge

Whether the capture event is interrupted when it occurs.

In the register description, 'n' indicates the number 0 or 1 of the timer. Each capture function is controlled by three digits.

The last thing left is some other registers related to timer 0 and 1.

1. Count control registers (t0ctr, t1ctr)

The Count control register is used to select the timing mode or counting mode, and in the counting mode, it is used to select the pin and edge count (rising or falling edge)

After the count mode is selected, capture the rising edge of the Input Pin (selected by ctcr [3: 2]) in each pclk for sampling. After comparing the sample values of two consecutive capture input pins, it is recognized as the rising and falling edges. Either of the edges or capture whether the level of the Input Pin has changed. The timer counter is added only when the events set in ctcr [1:0] are identified.

There are some limitations on the external clock provided to the counter. Because two consecutive rising edges of pclk are required to identify a change in the capture input pin, the input frequency of the capture Input Pin cannot exceed 1/2 of pclk. In this case, the duration of the high/low level must be no less than 1/pclk.

2. PWM control register (pwm0con, pwm1con)

This register is used to control the matching output as a PWM output. Each matching output can be set to PWM output independently. For each timer, up to three single-sided PWM outputs can be selected on matn.2: 0. Another matching register is used to determine the PWM output cycle. When any other matching Register matches, the PWM output is set to a high level. The timer can be selected as a matching register reset for the PWM cycle. When the timer is reset to 0, all PWM outputs are set to low.

The following is the rule for controlling the PWM output along a single side:

1. Except when the matching value is 0, the PWM output of all controls is low at the beginning of each PWM cycle (the timer is set to 0 at this time)

2. When the matching Register matches, the relevant PWM output will be set to high. If no matching occurs (for example, the matching value is greater than the PWM period), the PWM output will always output the low level

3. If the value of the matching register is greater than the PWM output period and the PWM output is high, the PWM output will be cleared when the timer is reset.

4. if the value of a matching register is the same as that of a PWM period, it will be reset after the next PWM cycle counting clock. Therefore, a PWM will be composed of a high level of the clock width, the width is determined by the PWM counting clock.

5. If the value of a matching register is 0, the first PWM output is a high level. At the same time, the timer remains high after the reset.

 

Next we will explain the timer interruption.

Two 32-bit timers are available for the lpc2103, and each timer can generate eight types of interruptions. 4-way matching interrupt and 4-way capturing interrupt. You can read the interrupt mark register (tnir) to differentiate the interrupt type. Is the relationship between timer interrupt and vector Interrupt Controller (Vic ).

1. Matching interruption

The timer overflow of the lpc2103 will not interrupt, but the matching can interrupt. Each timer has four matching registers to store matching values. When the timer's Count value TC is equal to Mr, an interruption occurs. The switch register tnmcr controls the Enable of matching interruption. Take the timer 0 as an example to describe the matching interruption:

2. Capture interruption

When a specific capture signal is displayed on the cap of the capture pin of the timer, interruption may occur. Taking cap0.0 as an example:

 

The above is all the content of timer 0 and timer 1, and it feels that the timer of the lpc2103 is quite powerful. To consolidate the knowledge of this section.

 

See easyarm2103

 

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