[Learning] basic principles of FPGA (may not be correct)

> What is FPGA?

 

FPGA, short for field programmable gate array, is a field programmable gate array. It is a product of further development on the basis of programmable devices such as pal, gal, and EPLD. As a semi-customized circuit in the field of specialized Integrated Circuits (ASIC), it not only solves the shortcomings of customized circuits, overcome the disadvantages of limited number of gate circuits of the original programmable device.
FPGA adopts a new concept such as logic cell array (LCA), which includes configurable logic modules CLB (Programmable Logic block) and output input module IOB (input output block) and interconnect. The basic features of FPGA include:

A) FPGA is used to design ASIC circuits. You can use the chips without generating chips.

B) FPGA can be used as a pilot Sample for other fully-customized or semi-customized ASIC circuits.

C) FPGA has a variety of internal triggers and I/O pins.

D) FPGA is one of the devices with the shortest design cycle, the lowest development cost, and the lowest risk in ASIC circuits.

E) FPGA adopts the high-speed chmos process, which has low power consumption and can be compatible with CMOS and TTL levels.

It can be said that FPGA chip is one of the best choices for small batch systems to improve system integration and reliability.

FPGA is set by the program stored in the On-chip RAM. Therefore, you need to program the on-chip RAM during work. Users can adopt different programming methods based on different configuration modes.

When power-on is enabled, the FPGA chip reads the EPROM data into the on-chip programming Ram. After the configuration is complete, the FPGA enters the working state. This process is called "loading" or "loading" in materials. Isn't it strange? Similar to bootrom in an arm-series chip, bootloader is loaded into internal SRAM. After power loss, FPGA becomes white, and the internal logic relationship disappears. As a result, FPGA can be used repeatedly. FPGA programming does not require a dedicated FPGA programmer. You only need to use a universal EPROM or prom programmer. When you need to modify the FPGA function, you only need to change an EPROM. In this way, different programming data of the same FPGA can generate different circuit functions. Therefore, FPGA is very flexible to use.

> LUT

 

Look-up-table (LUT) is essentially a ram. Currently, FPGA uses 4-input Lut, so each LUT can be regarded as a 16x1 RAM with 4-bit address lines. After you describe a logical circuit through a schematic or HDL language, the PLD/FPGA development software automatically calculates all possible results of the Logical Circuit and writes the results to ram in advance, each input signal performs a logical operation, which is equivalent to entering an address for table search, finding out the corresponding content of the address, and then outputting it.

The following is an example of 4 inputs and gates,

Actual Logic Circuit		Lut Implementation Method
Input a, B, c, d	Logical output	Address	Content stored in Ram
0000	0	0000	0
0001	0	0001	0
....	0	...	0
1111	1	1111	1

 

> Query table (LUT)-based FPGA Structure

 

Through the LUT description above, if you think you can use this to implement FPGA, congratulations, you are too smart.

Let's take a few FPGAs as an example to illustrate the LUT-based FPGA structure.

 

Let's take a look at the internal structure of Xilinx Spartan-II, such:

Internal Structure of Xilinx Spartan-II Chip	Slices Structure

Spartan-II mainly includes CLBs, I/O blocks, Ram blocks, and programmable connections (not expressed ). In Spartan-II, a CLB includes two slices. Each slices includes two LUTs, two triggers, and related logic. Slices can be viewed as the most basic structure of the spartanii implementation logic (Other Xilinx series, such as spartanxl and Virtex, have a slightly different structure. For details, see the data manual)

The structure of Intel's Flex/acex chips is as follows:

 

 

Internal Structure of Altera FLEX/acex Chip

 

 

 

Internal Structure of logical unit (LE)

The flex/acex structure mainly includes lab, I/O BLOCK, ram block (not expressed) and programmable row/column connections. In Flex/acex, a lab contains eight logical units (LE), each of which includes a Lut, a trigger, and related logic. Le is the most basic structure of the implementation logic of the Flex/acex chip (other generations of Altera, such as apex, have the same structure as this. For details, see the data manual)

 

> Basic working principle of LUT-structured FPGA

 

After power-on, the program is loaded into the FPGA's internal RAM, and then LUT can work. According to spec, this process is very fast and can be ignored. In the Military and aerospace FPGA, the program can be directly obtained to flash or EEPROM, without the need to load the process, to achieve the characteristics of power-on operation, similar to PLD.

Next we will describe the basic principles of FPGA Based on LUT structure.

 

Let's take this circuit as an example:

A, B, C, and D are input by the FPGA chip pins and then connected to LUT as address lines. LUT has written all possible logical results in advance, find the corresponding data through the address and then output the data, so that the combination logic is implemented. In this circuit, d triggers are directly implemented using the D triggers behind LUT. The clock signal CLK is input by the I/o foot and then enters the dedicated clock channel inside the chip, directly connected to the trigger's clock end. The trigger output is connected to the I/O pin, and the result is output to the chip pin. In this way, the PLD completes the function of the circuit shown in figure 3. (The above steps are automatically completed by the software without human intervention)

This circuit is a simple example. You only need a LUT and a trigger. For a circuit that cannot be completed by Lut, it is necessary to connect multiple units through the Carry Logic, so that FPGA can implement complex logic.

Because LUT is mainly suitable for the SRAM process production, most FPGAs are based on the SRAM process, and the information of the SRAM process chip will be lost after power loss. A dedicated configuration chip must be added, during power-on, the dedicated configuration chip loads the data into FPGA, and then the FPGA can work normally, because the configuration time is very short, it will not affect the normal operation of the system. There are also a few FPGAs that use the anti-fuse or Flash technology. For this FPGA, you do not need to add a dedicated configuration chip.

Because FPGAIt needs to be repeatedly written, and the basic structure of the combination logic cannot be completed by fixed and non-gate like ASIC, but can only adopt a structure that is easy to repeatedly configure. Lookup tables can meet this requirement. Currently, mainstream FPGAs use the SRAM-based or flash-based lookup table structure, repeated configuration of FPGA is achieved by changing the method of searching table content during each write operation.
So what is the principle of table substitution and non-gate circuit? We know that a logical operation of N input, whether it is a non-or non-operation or an exclusive or operation, can only have a maximum of 2n results. If we store the results in a storage unit in advance, isn't it equivalent to the actual function of the non-gate circuit? The principle of FPGA is exactly like this. It configures the table content by burning a file, so as to implement different logic functions under the same circuit.
Take example 1. Its truth table is shown in table 1. We only need to store the output y value in a 1x16 SRAM or flash, and then use A, B, C, and D for address index search and output, we can replace the gate operation, get the equivalent result.

[Example 1] A Four-input and gate circuit
Assign y = A & B & C & D;

Table 1 Example 1 corresponds to the truth table Input and Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1

 

> Valuable FPGA resource I/O resources: This determines the scalability of gpga; DCM: Digital Clock manager, which is used to achieve frequency doubling and can shake off; IP Core: this doesn't need to be said. Bram: it can be used to implement stack, FIFO, ram, and so on (I don't understand how to implement this, but I have never done it). Some of the above are my own summary and cannot be fully believed.