Lesson 3 make Makefile (I) and make makefile

Lesson 3 make Makefile (I) and make makefile
Preface:

The previous course explains the gcc compilation process to its practice. You can see that some of these steps can simplify compilation, however, due to the large number of parameters and the large number of files in the project, errors may occur, or even a lot of time is wasted on compilation. Therefore, this tool is also available in the linux system: makefile.

Principle:

In fact, the essence of Makefile files (usually starting with uppercase M) is a shell file that uses the specified rules to compile the file. Knowledge points are as follows:

 

The makefile tool uses its rules to execute commands. Generally, its contents are classified into macro definitions and commands. The simple macro definition is explained at the end. The command format is described first:

 

　　target ... : prerequisites ...　　　　command

The target file can be a. o file or an executable file;

Prerequisites is the dependent file required to generate the target. It can be a code file or a target file;

Command is the command executed by makefile. I forgot to thank Cui for reminding me that you must open the Tab key and enter it, And then reply to it;

This document describes how to use makefile.

Practice:

This lesson uses the original file calc. c. calc. h. calcmain. c3 files (For details, refer to them). First, clear other files and create a Makefile file. The steps are as follows:

1> Create a Makefile and enter the following content:

calc:calc.o calcmain.o     gcc -Wall calc.o calcmain.o -o calccalcmain.o:calcmain.c     gcc -Wall -c calcmain.c -o calcmain.ocalc.o:calc.c     gcc -Wall -c calc.c -o calc.o

.PHONY:clean

clean: rm calc.o calcmain.o calc

The first line in the code above:

Calc: calc. o calcmain. o: calc is the target of the Rule corresponding to the generated executable file; calc. o calcmain. o is the dependent file for generating the calc file;

Gcc-Wall calc. o calcmain. o-o calc: The command that meets the execution requirements;
Similarly, calcmain. o: calcmain. c: calcmain. o the target file depends on calcmain. c file, Note: If calcmain is modified separately. make calcmain. o and make calc commands run to generate the target file. After the operation, the link generates the executable file.

Gcc-Wall-c calcmain. c-o calcmain. o: generate the target file;
Finally, clean is a pseudo-target. Generally, add the following command before it to prevent the current directory from having the same command:

.PHONY:clean

2> now the Makefile file is ready. You can directly enter the make command to complete the compilation:

make

If you want to delete the generated file, execute:

make clean

If a single source file calcmain. c is modified, a single file calcmain. o is generated and linked to an executable file. The execution is as follows:

make clacmain.omake calc

This saves a lot of time when there are too many project files! This command is awesome, haha ......

3> careful readers can think of the problem that Makefile is a shell file and cannot be used to replace its content multiple times, this is really a good question. In fact, this is what we will talk about next. Calc: calc. o calcmain. o can I reduce the maintenance workload if I use variables in the subsequent target files? Can I replace the executable files with variables? The two problems are solved now, the new Makefile is as follows:

EXE=calcOBJECTS=calcmain.o calc.o $(EXE):$(OBJECTS)       gcc -Wall $^ -o $EXEcalcmain.o:calcmain.c      gcc -Wall -c $< -o $@calc.o:calc.c      gcc -Wall -c $< -o $@clean:      rm -f $(EXE) $(OBJECTS)

In this way, some predefined variables such as $ ^ are all dependent files; $ <is the first dependent file; $ @ is the current target object. This makes maintenance easier when there are many files.

Here is a lesson. You can find some predefined variables on the Internet.
Makefile creation Problems

This is basically the case for a simple Makefile.
GCC = gcc
A. o: a. cpp
$ (GCC)-c a. cpp

B .o: B .cpp
$ (GCC)-c B. cpp

OBJ = a. o B. o
AB: $ (OBJ)
$ (GCC)-o AB $ (OBJ)

AB

Make: Execute AB.

What is the role of makeFile?

Its functions are as follows:
Makefile is related to the compilation rules of the entire project. The source files in a project are not counted. They are stored in several directories by type, function, and module. makefile defines a series of rules to specify which files need to be compiled first, which files need post-compilation, which need to be re-compiled, or even perform more complex functional operations, because makefile is like a Shell script and can also execute operating system commands.
The benefit of makefile is "automatic compilation". Once written, only one make command is required, and the entire project is fully automatically compiled, which greatly improves the efficiency of software development.
Remember to like one.