Preface:
The previous course explains the GCC compilation process to its practice. You can see that some of these steps can simplify compilation, however, due to the large number of parameters and the large number of files in the project, errors may occur, or even a lot of time is wasted on compilation. Therefore, this tool is also available in the Linux system: makefile.
Principle:
In fact, the essence of makefile files (usually starting with uppercase m) is a shell file that uses the specified rules to compile the file. Knowledge points are as follows:
The makefile tool uses its rules to execute commands. Generally, its contents are classified into macro definitions and commands. The simple macro definition is explained at the end. The command format is described first:
target ... : prerequisites ... command
The target file can be a. o file or an executable file;
Prerequisites is the dependent file required to generate the target. It can be a code file or a target file;
Command is the command executed by makefile;
This document describes how to use makefile.
Practice:
This lesson uses the original file Calc. c. Calc. h. calcmain. c3 files (For details, refer to them). First, clear other files and create a MAKEFILE file. The steps are as follows:
1> Create a makefile and enter the following content:
calc:calc.o calcmain.o gcc -Wall calc.o calcmain.o -o calccalcmain.o:calcmain.c gcc -Wall -c calcmain.c -o calcmain.ocalc.o:calc.c gcc -Wall -c calc.c -o calc.o
.PHONY:clean
clean: rm calc.o calcmain.o calc
The first line in the code above:
Calc: Calc. O calcmain. O: calc is the target of the Rule corresponding to the generated executable file; Calc. O calcmain. O is the dependent file for generating the calc file;
Gcc-wall Calc. O calcmain. O-o calc: The command that meets the execution requirements;
Similarly, calcmain. o: calcmain. c: calcmain. O the target file depends on calcmain. c file, Note: If calcmain is modified separately. make calcmain. O and make calc commands run to generate the target file. After the operation, the link generates the executable file.
Gcc-wall-C calcmain. C-o calcmain. O: generate the target file;
Finally, clean is a pseudo-target. Generally, add the following command before it to prevent the current directory from having the same command:
.PHONY:clean
2> now the MAKEFILE file is ready. You can directly enter the make command to complete the compilation:
make
If you want to delete the generated file, execute:
make clean
If a single source file calcmain. C is modified, a single file calcmain. O is generated and linked to an executable file. The execution is as follows:
make clacmain.omake calc
This saves a lot of time when there are too many project files! This command is awesome, haha ......
3> careful readers can think of the problem that makefile is a shell file and cannot be used to replace its content multiple times, this is really a good question. In fact, this is what we will talk about next. Calc: Calc. O calcmain. O can I reduce the maintenance workload if I use variables in the subsequent target files? Can I replace the executable files with variables? The two problems are solved now, the new makefile is as follows:
EXE=calcOBJECTS=calcmain.o calc.o $(EXE):$(OBJECTS) gcc -Wall $^ -o $EXEcalcmain.o:calcmain.c gcc -Wall -c $< -o [email protected]calc.o:calc.c gcc -Wall -c $< -o [email protected]clean: rm -f $(EXE) $(OBJECTS)
In this way, some predefined variables such as $ ^ are all dependent files; $ <is the first dependent file; [email protected] is the current target object. This makes maintenance easier when there are many files.
Here is a lesson. You can find some predefined variables on the Internet.