Linux core-7. PCI device

Article title: Linux core-7. PCI device. Linux is a technology channel of the IT lab in China. Includes basic categories such as desktop applications, Linux system management, kernel research, embedded systems, and open source.
Original: David A Rusling
Translation: Banyan & fifa
Chapter 6 PCI
Peripheral device interconnection (PCI) is a bus standard that connects external devices in the system in a structured and controllable manner, including the electrical characteristics and behavior of system component connections. This chapter will discuss in detail the initialization process of the Linux core for the system's PCI bus and equipment.
. 1. a PCI-based system
. 1 is a PCI-based system. PCI bus and PCI-PCI bridge play a key role in connecting devices to the system, in which CPU and video devices are connected to PCI bus 0, which is the backbone of the system PCI bus. The PCI-PCI Bridge, a special PCI device, connects the trunk bus PCI bus 0 with the lower bus PCI bus 1. In PCI standard terminology, PCI bus 1 is the downstream of the PCI-PCI Bridge and PCI bus 0 is the up-stream of the bridge. SCSI and Ethernet devices are connected to the system through the second-level PCI bus. In terms of physical implementation, the bridge adapter and the secondary PCI bus are integrated into a PCI card. While the PCI-ISA bridge is used to support the old ISA device, there is an advanced I/O control chip in the figure to control the keyboard, mouse and floppy disk devices.
6.1 PCI address space
The CPU and PCI devices need to access the shared memory space between them. The memory area is driven by the device to control the PCI device and transmit information between the CPU and the PCI device. The most typical shared memory includes device control and status registers. These registers are used to control the device and read its information. For example, the pci scsi device driver can read its status register to find the SCSI device that is ready to write a piece of data to the SCSI disk. You can also enable the device by writing information to the control register after the device is powered on.
CPU system memory can be used as this shared memory, but if this method is used, the CPU is forced to stop working every time the PCI device accesses this memory block, waiting for the PCI device to complete this operation. In this way, the shared memory is limited to allowing access from only one system device at a time. This policy greatly reduces system performance. However, it is not a good solution to allow unrestricted access to the primary memory. The danger is that a malicious device puts the entire system in an unstable state.
Peripherals have their own memory space. The CPU can freely access this space, but the access from the device to the system's primary storage is strictly controlled by the DMA (direct memory access) channel. The ISA device needs to access two address spaces: isa I/O (input/output) and ISA memory. The PCI device needs to access three address spaces: pci I/O, PCI memory, and PCI configuration space. The CPU can access all these address spaces. Pci I/O and PCI memory are used by the device driver, while the PCI configuration space is used by the PCI initialization code in the Linux core.
The Alpha AXP processor cannot freely access these address spaces as it accesses the system address space. it can only access these address spaces through the auxiliary chipset, such as the PCI configuration space. The Alpha AXP processor uses a sparse address ing policy to "steal" a portion of the system's huge virtual memory and map it to the PCI address space.
6.2 PCI configuration header
. 2 PCI configuration header
Each PCI device in the system, including the PCI-PCI Bridge, has a configuration data structure that is typically located in the PCI configuration address space. The PCI configuration header allows the system to identify and control devices. The position of the configuration header in the PCI configuration space depends on the topological structure of the PCI device in the system. For example, if you insert a PCI video card into a different PCI slot, the configuration header position will change. But it does not affect the system. The system will find each PCI device and the bridge and use the information in their configuration header to configure its registers.
A typical method is to determine the offset of the PCI configuration header in the configuration space by using the position of the PCI slot relative to the motherboard. For example, the PCI configuration header of the first PCI slot in the motherboard is located at 0 of the configuration space offset, and the second is located at 256 of the offset (all PCI configuration headers are of the same length, which is 256 bytes ), other slots can be inferred. The system also provides a hardware-related mechanism so that the PCI configuration code can correctly identify the PCI configuration headers of all existing devices on the corresponding PCI bus. The domain in the PCI configuration header is used to determine which devices exist and which devices do not exist (this domain is called the Vendor flag domain: Vendor Identification field ). An error message with the value of 0xFFFFFFFF is returned for the read operation on this field in the empty PCI slot.
. 2. the structure of the 256-byte PCI configuration header is given. it contains the following fields:
Vendor Identification)
The value that uniquely identifies the manufacturer of the PCI device. Digital's PCI vendor ID is 0x1011 while Intel's ID is 0x8086.
Device Identification)
The value that uniquely identifies a device. The device ID of the Digital 21141 Fast Ethernet device is 0x0009.
Status)
This domain provides the status information for this device in the PCI standard definition.
Command)
You can control this device by writing this domain, for example, allowing devices to access pci I/O memory.
Class Code)
This field identifies the type of the device. Standard classification codes are available for each type of video or SCSI devices. For example, the SCSI device classification code is 0x0100.
Base Address Registers)
These registers are used to determine and allocate the types, quantities, and locations of the pci I/O and PCI memory space that the device can use.
Interrupt Pin)
The four physical pins on the PCI card can take the interrupt signal from the plug-in card to the PCI bus. The four pins are marked as A, B, C, and D. The interrupt pin field describes the PIN numbers used by the PCI device. Usually, specific devices are hard-connected. This is also the reason that the device always uses the same interrupt pin when the system starts. The interrupt processing subsystem uses it to manage interruptions from this device.
Interrupt Line)
The interrupt connection field in the device configuration header is used to transmit the interrupt processing process between the PCI initialization code, the device driver, and the Linux interrupt processing subsystem. Although the value recorded in this domain is meaningless to the device driver. However, it can route the interrupt handling process from the PCI card to the corresponding device driver interrupt handling code in the Linux operating system. The Linux interrupt handling process is described in detail in the interrupt chapter.
6.3 pci I/O and PCI memory addresses
These two address spaces are used to implement communication between the PCI device and the device driver in the Linux core. For example, when the internal registers of the DEC21141 Fast Ethernet device are mapped to the pic I/O space, the corresponding Linux device driver can control the device by reading and writing these registers. PCI video cards usually use a large amount of PCI memory space to store video information.
The system will not allow access to these address spaces until the PCI system establishes and opens these address spaces by using the command domain in the PCI configuration header. It is worth noting that only the PCI configuration code reads and writes the PCI configuration space, and the Linux device driver read-only writes the pci I/O and PCI memory addresses.
6.4 PCI-ISA Bridge
This bridge converts the access to the pci I/O and PCI memory space into the access to the isa I/O and ISA memory to support the ancient ISA device. Many main boards on the market contain several ISA cable slots and PCI slots at the same time. However, in the future, the backward compatibility of the ISA device will gradually decrease, and only the pci will be available on the motherboard. The early Intel 8080 PC fixed the ISA address space of the ISA device. Even in Alpha AXP Systems worth US $5000, the ISA floppy controller address is the same as that on the oldest ibm pc. The PCI standard retains the low-end portion of the pci I/O and PCI memory to the ISA peripherals in the system, and also converts from PCI memory access to ISA memory access using a PCI-ISA Bridge.
6.5 PCI-PCI Bridge
The PCI-PCI Bridge is a special PCI device that connects all the PCI bus in the system. In a simple system, only one PCI bus exists. due to the limitation of electrical characteristics, the number of PCI devices connected to it is limited. After the PCI-PCI Bridge is introduced, the system can use more PCI devices. This is very important for high-performance servers. Linux provides comprehensive support for the PCI-PCI Bridge.
6.5.1 PCI-PCI Bridge: pci I/O and PCI memory windows
The PCI-PCI bridge transfers a subset of pci I/O and PCI memory read/write requests down. For example. 1. if the request from PCI bus 0 is read/write to the pci I/O or PCI memory owned by SCSI or Ethernet devices, the PCI-PCI Bridge will simply pass requests from bus 0 to PCI bus 1; all other pci I/O and memory addresses will be ignored by it. This filter prevents the address information from spreading across the system. To achieve this, the PCI-PCI bridge must be programmed to have a certain pci I/O and PCI memory base address and upper limit, only access from the PCI address within this address range can be transferred from the trunk bus to the secondary bus. Once the PCI-PCI bridge in the system is set to this, the PCI-PCI Bridge becomes transparent as long as the Linux device driver accesses the pci I/O and PCI memory space through this window. In this way, the Linux PCI device driver writer is also provided with convenience. We will see a very clever configuration of the PCI-PCI Bridge in Linux later on.
6.5.2 PCI-PCI Bridge: PCI configuration cycle and PCI bus serial number
. 3 0 type PCI configuration cycle
. 4 type 1 PCI configuration cycle
To enable the PCI initialization code running on the CPU to access the device on the branch PCI bus, A certain mechanism must be provided for the bridge adapter so that it can decide whether to pass the configuration loop from the trunk interface to its second-level interface. Loop is an address that appears on the PCI bus. The PCI standard defines two PCI configuration addressing formats: Type 0 and type 1, as shown in 6.3 and 6.4, respectively. Type 0 PCI configuration cycle does not contain the bus serial number, and all PCI devices corresponding to the PCI configuration address on this PCI bus will explain them. Type 0: The 11-to-31 bits of the configuration cycle are used to select the PCI device. There is a way to design a device that represents a different device in the system. At this time, 11 bits correspond to the PCI device in PCI slot 0 and 12 bits mark the device in slot 1, and so on. Another method is to directly write the Slot Number of the device into place 31 to 11. Which mechanism does the system use depends on the system PCI memory controller.
Type 1 PCI configuration cycle contains a PCI bus serial number, which is ignored by all PCI devices except the bridge. All Discovery type 1 configuration loop PCI-PCI bridges pass the addresses they see to their respective lower-level PCI bus. Whether the PCI-PCI Bridge ignores the Type 1 configuration loop or passes it to the PCI bus depends on how the PCI-PCI Bridge is configured. Each PCI-PCI bridge has a trunk bus interface number and a secondary bus interface number. The trunk bus is the PCI bus closest to the CPU, while the secondary bus is the PCI bus a little farther away from it. Any PCI-PCI Bridge also contains a secondary bus serial number, which is the largest of all the secondary bus interfaces that bridge the PCI bus. Or the subordinate bus number is the maximum number of the PCI bus that the PCI-PCI Bridge connects down. When the PCI-PCI Bridge sees the Type 1 PCI configuration loop, it performs the following operations:
If the bus serial number is not between the second-level bus serial number of the bridge adapter and the slave bus serial number, ignore it.
If the bus serial number is the same as the second-level bus serial number of the bridge, convert it to type 0 configuration command.
If the bus serial number is in the bridge