Linux interrupt mechanism

Pc/at microcomputer Cascade type 8259 control system

The 8259 is introduced as part of the Intel's MCS family in 1976. The 8259A was included in the original PC introduced in 1981 and maintained by the PC/XT when introduced in 1983. A second 8259A was added with the introduction of the Pc/at. The 8259 have coexisted with the Intel APIC Architecture since their introduction in symmetric multi-processor PCs. Modern PC S has begun to phase out the 8259A in favor of the Intel APIC Architecture. However, while not anymore a separate chip, the 8259A interface are still provided by the Southbridge chipset on modern x86 Motherboards.

The main signal pins on an 8259 is as follows:eight interrupt input request lines named IRQ0 through IRQ7, an interrupt Request output line named INTR, interrupt acknowledgment line named INTA, D0 through D7 for communicating the interrupt Le Vel or vector offset. Other connections include CAS0 through CAS2 for cascading between 8259s.

Up to eight slave 8259s is cascaded to a, master 8259 to provide, to-IRQs. 8259s is cascaded by connecting the int. line of one slave 8259 to the IRQ line of one master 8259.

There is three registers, an Interrupt Mask register (IMR), a Interrupt Request register (IRR), and an in-service regist ER (ISR). The IRR maintains a mask of the current interrupts that is pending acknowledgement, the ISR maintains a mask of the Inter Rupts that is pending an EOI, and the IMR maintains a mask of interrupts the should is not being sent an acknowledgement.

End of Interrupt (EOI) Operations support specific EOI, non-specific EOI, and Auto-eoi. A specific EOI Specifies the IRQ level it's acknowledging in the ISR. A non-specific EOI Resets the IRQ level in the ISR. AUTO-EOI resets the IRQ level in the ISR immediately after the interrupt is acknowledged.

Edge and level interrupt trigger modes is supported by the 8259A. Fixed priority and rotating priority modes is supported.

The 8259 is configured to work with a 8080/8085 or an 8086/8088. On the 8086/8088, the interrupt controller would provide an interrupt number on the data bus when an interrupt occurs. The interrupt cycle of the 8080/8085 would issue three bytes on the data bus (corresponding to a call instruction in the 80 80/8085 instruction Set).

The 8259A provides additional functionality compared to the 8259 (in particular buffered mode and level-triggered mode) an D is upward compatible with it.

From

Interrupt signals are usually divided into two categories: hardware interrupts and software interrupts, int 0x0 ~ int 0x1F belongs to software interrupt (exception) [Fault + trap], and in Linux, the 0x20 ~ 0x2F corresponds to the hardware request signal from the 8259A interrupt control chip IRQ 0x0 ~ IR Q 0xF, and set the program to send the system call interrupt to int 0x80

In Linux, the kernel first uses a dummy interrupt vector (interrupt descriptor) to set the default for all 256 descriptors of the interrupt descriptor, which points to a default "non-disruptive" process.

hardware exceptions (int 0x0 ~ int 0x01f) are processed in the file traps.c

System call Interrupt int 0x80 is initialized in SCHED.C.

Linux interrupt mechanism