0. PrefaceFrom the beginning of learning C language began to contact Makefile, consulted a lot of makefile information but always feel no real master makefile, if you write a makefile always feel very laborious. So deliberately using the blog to summarize the relevant knowledge of makefile, through examples to illustrate the specific use of makefile. The example says that makefile roughly divides into 4 parts 1. Only a single C file 2. Contains multiple C files 3. The header file path 4 needs to be included. A more complex example of the "code warehouse"--makefile-example code warehouse is located in BitBucket, You can clone the code with TORTOISEHG (GUI tools) or download the zip package directly from the Web page.
1. Review GCC directivesA very simple C file--test.c"TEST.c"
#include <stdio.h>int main (void) { int a = 3; int b = 2; printf ("a=%d\n", a); printf ("b=%d\n", b); return 0;}
"The simplest way"GCC Test.c-o test eventually generates an executable fileTest。 "Execute test"./test "Output results" a=3 b=5"incorrect wording."Please note that the following wording is not correct. Gcc-c Test.c-o Test
"Detailed Step Decomposition" compilation--LinksNo matter how the parameters of the GCC directive change, it takes only two steps to make the executable file from the source file, the first step of the source filecompilingAs the target file, the second step from the target filelinksAs an executable file. In the simplest instruction--GCC Test.c-o test uses a gcc implicit rule, and all of the two key steps for compiling and linking are not apparent. Then the following instructions let "not obvious" become "obvious". "1" compiled by C file to target file"notation 1"Gcc-c Test.c-o TEST.O"2"--order can be reversedgcc-o test.o-c test.c"3"--appropriate shorthandThe *.O file is compiled with the *.c file of the same name, as appropriate, using the default rules of GCC. Gcc-c test.c"4"--a little strange .This can also be written, although it looks a bit strange, but only the results are the same. Makefile files seem to prefer this way. Gcc-c-O test.o test.c
"2" link the target file to an executable file"notation 1"GCC Test.o-o Test"2"--order can be reversedThe order can be reversed, and the makefile file seems to prefer this way. Gcc-o Test TEST.O
2. Writing the makefile file"Makefile"Replace [tab] with the makefile file in the code warehouse.
# executable target = test# dependent destination OBJS = test.o# directive compiler and options cc=gcccflags=-wall-std=gnu99$ (target): $ (OBJS) # @echo Target:[email Prot ected]# @echo objects:$^ [tab]$ (CC)-o [email protected] $^clean: [Tab]rm-rf $ (TARGET) $ (OBJS)
"Specific Instructions""1" target=test test is the last executable, the executable file in Linux is the exe file in Windows"2" OBJS = TEST.O test.o corresponds to test.c, using Makefile's implied rules, TEST.O compiled by TEST.C. "3" CC=GCC specifies the compiler for GCC "4" cflags=-wall-std=gnu99 enable all warnings, specifying compiler standard for GNU99 "5" $ (CC)-o [email protected] $^ [E Mail protected] and $^ are automation variables, [email protected] refers to the target file, where the executable file test,$^ refers to the removal of duplicate dependent files, here is TEST.O $ (CC)-o [email protected] $^ final change to Gcc-o test TEST.O. The instructions in the Gcc-o test TEST.O and the "Detailed steps" link sections are identical. Then the makefile and the GCC directive established a connection. You can debug makefile Acceleration error correction in this way by printing automation variables during makefile execution through the @echo directive.
"Compile"Make clean && make do clean before executing make build executable file
"Console Output"Gcc-wall-std=gnu99-c-o test.o test.cgcc-o test TEST.O
"Analysis"If you remove-wall-std=gnu99, then the above two sentences are simplified to gcc-c-O TEST.O test.c and the compilation Process method "4" the same Gcc-o test TEST.O and the execution process method "2" the same then makefile and GCC The directive establishes the relationship, and the understanding is much more convenient.
3. Further refine some"Makefile"Replace [tab] with the makefile file in the code warehouse as the main
# executable file target=test# c file SRCs = test.c# destination File Objs = $ (SRCS:.C=.O) # instruction compiler and options cc=gcccflags=-wall-std=gnu99$ (target): $ (OBJS) # @echo target:[email protected]# @echo objects:$^ [tab]$ (CC)-o [email protected] $^clean: [Tab]rm-rf $ (TARGET) $ (OBJS)%.O: %.c [tab]$ (CC) $ (CFLAGS)-o [email protected]-C $<
"Change description" "1" OBJS = $ (SRCS:.C=.O) There is no re-enactment of the rules using GCC's default rules to prepare for later joining the header file lookup path. The "2" $< is an Automation variable, which refers to the first target file, after the test.c substitution variable and the automation variable: test.o:test.c [tab]gcc-wall-std=gnu99- o test.o-c test.c
4. Summary"1" gcc Command execution order--Compile the target file first, then link it to the executable "2" automation variable [email protected] The target file of the current rule $< the first dependent file $^ Remove all dependent files for duplication
