0. PrefaceFrom the beginning of learning C language began to contact Makefile, consulted a lot of makefile information but always feel no real master makefile, if you write a makefile always feel very laborious. So deliberately using the blog to summarize the relevant knowledge of makefile, through examples to illustrate the specific use of makefile. The example says that makefile roughly divides into 4 parts 1. Only a single C file 2. Contains multiple C files 3. Need to include header file path 4. Add a macro definition 5. Add a system Shared library 6. Add a custom shared Library 7. A practical example of "code warehouse"-- The Makefile-example code warehouse is located in BitBucket and can be cloned with TORTOISEHG (GUI tools) or downloaded directly from a Web page. "This example explains"
This example explains how to include a macro definition in the makefile file.
1.GCC ReviewThe macro definition uses the prefix-D to append the macro definition to Cflag during compilation. The macro definition has two similar wording "the first"-D defines "the second"-D defines=condition
2. Source FilesUse #ifdef and # If in two different ways to define the parcel printing function with macros
#include <stdio.h> #include <test-add.h> #include <test-sub.h>int main (void) { int a = 3; int b = 2; printf ("a=%d\n", a); printf ("b=%d\n", b), #ifdef test_add printf ("a+b=%d\n", ADD (b)), #endif # if test_sub printf ("a-b=%d\n", SUB ( A, b)); #endif return 0;}
3.makefileReplace [tab] with the makefile file in the code warehouse.
# directive compiler and Options cc=gcccflags=-wall-std=gnu99# macro definition DEFS =-dtest_add-dtest_sub=1cflags + = $ (DEFS) # destination file target=test# source file SRCs = test.c ./test-add/test-add.c ./test-sub/test-sub.c# header File Find path inc =-i./test-add-i./test-sub# Destination file Objs = $ (SRCS:.C=.O) # link as executable $ (target): $ (OBJS) # @echo Target:[email protected]# @echo objects:$^[tab]$ (CC)-O [ Email protected] $^CLEAN:[TAB]RM-RF $ (target) $ (OBJS) # Continuous action, clear the recompile link, and finally execute Exec:clean $ (target) [tab] @echo start execution [tab]./$ ( target) [tab] @echo execution End # compilation rule [email protected] represents the target file $< on behalf of the first dependent file%.o:%.c[tab]$ (CC) $ (CFLAGS) $ (INC)-O [email protecte D]-C $<
4. Specific Instructions
The "1" makefile defines a header file in two ways
"First Type"-D defines
"Second Type"-D defines=condition
The first of these methods corresponds to
#ifdef
Do_something ()
#endif
The second method corresponds to
#ifndef defines
Do_something ()
#endif "2" DEFS =-dtest_add-dtest_sub=1 in order to illustrate the problem, two different ways of writing are used here. At this point the two printing functions are executed "3" CFLAGS + = $ (DEFS) appended to CFLAGS, where you need to emphasize that CFLAGS is just a variable, can be named any legitimate name, as long as the compilation process to reference the parameter. $ (CC)$ (CFLAGS)$ (INC)-o [email protected]-C $<
5. Execution Process"Compile and link" make clean && make "console output" RM-RF test TEST.O./test-add/test-add.o./test-sub/test-sub.o
Gcc-wall-std=gnu99-dtest_add-dtest_sub=1-i./test-add-i./test-sub-o test.o-c test.c
Gcc-wall-std=gnu99-dtest_add-dtest_sub=1-i./test-add-i./test-sub-o test-add/test-add.o-c TEST-ADD/TEST-ADD.C
Gcc-wall-std=gnu99-dtest_add-dtest_sub=1-i./test-add-i./test-sub-o test-sub/test-sub.o-c TEST-SUB/TEST-SUB.C
Gcc-o Test TEST.O TEST-ADD/TEST-ADD.O test-sub/test-sub.o The output from the console shows that the-D parameter was added to the compilation process. "Execution" a=3
b=2
A+b=5
A-b=1The final effect is exactly the same as expected, and makefile gets the validation.
6. Summary"1" Add two methods for macro definition-D defines and-D defines=condition "2" macro definition appended to Cflag
