Linux makefile entry instance

Purpose:

I have mastered the usage of make and can program on Linux.
Environment:
Linux system, or a Linux server, connected through a terminal. One sentence: There is a Linux compiling environment.
Preparation:
Prepare three files: file1.c, file2.c, and file2.h.

File1.c:

# Include <stdio. h>

# Include "file2.h"

Int main ()

{

Printf ("Print file1 $ \ n ");

File2print ();

Return 0;
}

File2.h:

# Ifndef file2_h _
# Define file2_h _

# Ifdef _ cplusplus

Extern "C "{

# Endif

Void file2print ();

# Ifdef _ cplusplus

}

# Endif

# Endif

File2.c:

# Include "file2.h"

Void file2print ()

{

Printf ("Print file2 *********************** \ n ");
}

Basics:

Here is an example:

There is such a makefile. (The file and makefile are in the same directory)
=== Makefile start ===

Helloworld: file1.o file2.o

GCC file1.o file2.o-O helloworld

File1.o: file1.c file2.h

Gcc-C file1.c-O file1.o

File2.o: file2.c file2.h

Gcc-C file2.c-O file2.o

Clean:

Rm-RF *. O helloworld

=== Makefile
End ===

A makefile
It mainly contains a series of rules as follows:
A: B
(Tab) <command>
(Tab) <command>

Each command line must have a tab.

 

The makefile above aims to compile an executable helloworld file. Let's explain in one sentence:

Helloworld: file1.o file2.o:
Helloworld depends on two target files: file1.o file2.o.

GCC file1.o file2.o-O helloworld:
Compile the helloworld executable file. -O indicates that you specify
Target file name.

File1.o: file1.c:
File1.o depends on the file1.c file.

Gcc-C file1.c-O file1.o:
Compile the file1.o file. -C indicates gcc
Only compile the file for it into the target file. Use the name of the source file, but change its Suffix from ". c" or ". cc" to ". O ". -O file1.o can be omitted in this sentence. By default, the compiler generates the file1.o file, which is the role of-C.

 

File2.o: file2.c file2.h
Gcc-C file2.c-O file2.o

These two sentences are the same as the previous two sentences.

 

Clean:

Rm-RF *. O helloworld

*. O is deleted when you type the make clean command.
And the helloworld file.

 

To compile the CPP file, you only need to change GCC to G ++.

Write the MAKEFILE file, and directly type the make command in the command line to execute the content in the makefile.

 

In this step, I think you can compile a helloworld program.

 

Previous floor: Use Variables

As mentioned above, if you want to compile the CPP file, you just need to change GCC to G ++. However, if there are many GCC in makefile, it will not be very troublesome.

Example 2:

=== Makefile
Start =
Objs = file1.o file2.o
Cc = gcc
Cflags =-wall-o-g

Helloworld: $ (objs)
$ (CC) $ (objs)-O helloworld

File1.o: file1.c file2.h
$ (CC) $ (cflags)-C file1.c-O file1.o

File2.o: file2.c file2.h
$ (CC) $ (cflags)-C file2.c-O file2.o

 

Clean:

Rm-RF *. O helloworld
=== Makefile ended ===

 

Here we apply the variable. To set a variable, you only need to write the variable name at the beginning of a line.
It is followed by a = sign, followed by the value of the variable you want to set. You will reference it later
This variable is written with a $ symbol followed by the variable name enclosed in brackets.

 

Cflags =-wall-o-g. This is to configure the compiler settings and assign it to the cfflags variable.

-Wall:
Output all warning information.

-O:
Optimized during compilation.

-G:
Indicates compiling the debug version.

 

In this way, the MAKEFILE file is relatively simple, but it is easy to find the disadvantage, that is, to list all the C files. If you add a c file, you need to modify the MAKEFILE file, which is still troublesome in project development.

 

 

Next floor: Use Functions

After learning this, you may say, is it like programming? There are variables and functions. In fact, this is programming, but it only uses different languages.

Example 3:

=== Makefile
Start =
Cc = gcc

Xx = g ++
Cflags =-wall-o-g

Target =./helloworld

%. O: %. c

$ (CC) $ (cflags)-C $ <-o $ @

%. O: %. cpp

$ (XX) $ (cflags)-C $ <-o $ @

 

Sources = $ (wildcard *. C *. cpp)
Objs =$ (patsubst %. C, %. O, $ (patsubst %. cpp, %. O, $ (sources )))

$ (Target): $ (objs)
$ (XX) $ (objs)-o $ (target)

Chmod A + x $ (target)

Clean:

Rm-RF *. O helloworld
=== Makefile ended ===

Function 1: wildcard

Generate'
The list of objects at the end.

Sources = $ (wildcard *. C *. cpp) indicates that a list of all files ending with. C and. cpp is generated, and then saved to the sources variable.
.

 

Function 2: patsubst

Match and replace. There are three parameters. The first is a pattern to be matched, the second represents what to replace it with, and the third is a list to be processed separated by spaces.

Objs = $ (patsubst %. c, %. o, $ (patsubst %. CC, %. o, $ (sources) indicates all files in the list. C ,. CPP character. o to form a new file list and store it in the objs variable.

 

%. O: %. c

$ (CC) $ (cflags)-C $ <-o $ @

%. O: %. cpp

$ (XX) $ (cflags)-C $ <-o $ @

These commands compile all. C and. cpp into a. o file.

There are three useful internal variables. $ @
Extended to the target file name of the current rule, $ <extended to rely on
The first dependent file in the list, and $ ^ expands to the entire dependent list (removing all the duplicates in the list
File name ).

 

Chmod A + x $ (target) indicates that helloworld is forced into an executable file.

Now, I think you can write a simple and general MAKEFILE file. All the examples above assume that all files are in the same directory, excluding subdirectories.

Is it possible that the file is not in a directory?

How to compile makefile to generate a static library?

Do you still want to take it to another level?

Listen to the next decomposition.

Source: http://www.cnblogs.com/goodcandle/archive/2005/11/17/278702.html