Linux programming _ MAKEFILE file

 

Linux programming-MAKEFILE file

Today I want to talk about this MAKEFILE file. makefile? I did not get this stuff on the Windows platform. In fact, there are also some, but we are not in touch with it.

Makefile. What is it? What is the purpose? How to write? This is what I want to talk about.

We all know that developing a program in the traditional C and C ++ languages requires the following steps: Edit, compile, and connect. The connection runs successfully. On the Windows platform, these steps are automatically completed with the help of development tools, so we are not very impressed. On the Linux platform, we need to follow this process by ourselves (this sentence is not very correct, and there are already some development tools on Linux ). Well, it seems that the MAKEFILE file is closely related to this process.

For example, print "Hello World!" on a Linux terminal !".
My machine is redhat9.0, And the compiler uses g ++ 3.0.
Edit a main. cpp file with the following content:

# Include <iostream>

Int main (INT argc, char ** argv ){

Printf ("Hello, world! /N ");

Return 0;
}

After editing, you should compile the code. Enter the directory where the code file is located from the terminal and execute the following command:

# G ++-wall-O2-C main. cpp
# Is a command prompt. For the usage of G ++ commands and the significance of each parameter, please refer to other books. I will not describe this too much here.
After this command is executed, the directory contains an additional main. o file. The appearance of this file illustrates some problems. For our developers, there is no syntax error in our source code! If there is a syntax error, the compiler will print the error information to the terminal window. If not, modify the code, save the modification, and then run the preceding command.

After the compilation is passed, this is not a small step. Then the connection is completed. Execute the following command:

# G ++ main. O-o main.exe

This command connects main.oto mian.exe. In a project, a running file is connected by many. O files and other library files provided by the operating system. It is not as simple as here. At this time, a main.exe file is displayed in the directory. Check the attributes of the file and you can see that it has the running attributes. By the way, this is the final executable file we want. If the value is correct, the main.exe file name here is arbitrarily specified. The system will not assign the running attribute to it because we add an EXE suffix, Nor will this running attribute be canceled without the EXE suffix.

Okay. Run the file:

#./Main.exe

Press enter to view the "Hello World!" printed on the terminal !" .
Now I have some functions in another file, in Main. use these functions in the CPP file. For example, the other code files are funtion. H and function. CPP file, in Main. the CPP file must contain funtion. h file (# include "function. H "), and then
Run the following command:

# G ++-wall-O2-C function. cpp
# G ++-wall-O2-C main. cpp

When both the function. o file and the main. o file exist, connect

# G ++ main. O function. O-o main.exe

Now, the new main.exe file is connected.
If funtion. H and function. if the content in the CPP file is changed, the funtion will be re-compiled. o file, dependent on funtion. H and function. main. the CPP file also needs to be compiled, and the connection needs to be done more. It is annoying. If there are many code files, the dependency (Inclusion) relationship is complicated, and a file is modified, which one. O files need to be re-compiled, compiled, and re-connected. This is tedious and error-prone, and the operation is unrealistic.

What should I do? Look! The MAKEFILE file appears.

Makefile is a shell file (called in Linux, equivalent to a batch file in windows. BAT), which records the dependency between code files. The MAKEFILE file determines which file needs to be re-compiled.

Let's first look at a specific MAKEFILE file:

# ----------------------- Start of makefile ------------------------
Cc = g ++
Cflags =-wall-O2-G-d _ debug __
Primary des =-I.
Libs =-lpthread
Objs = thread. O crc32.o ts. O tspacketizer. O utils. O socket. o pdg. O test_pdg.o

Prog = pdgd

%. O: %. cpp
$ (CC) $ (cflags) $ (DES)-C $ <

ALL: $ (Prog)

$ (Prog): $ (objs)
$ (CC) $ (libs) $ (objs)-o $ (Prog)

Clean:
Rm-f *. o $ (Prog)
 
Install:
CP./pdgd/usr/sbin/
CP./pdg_tester/etc/init. d/
Chmod + x/etc/init. d/pdg_tester

# ----------------------- End of makefile ---------------------------

The line starting with "#" in the MAKEFILE file is equivalent to the annotation and does not work.

The following is a rough explanation:
Cc = g ++ indicates that the compiler used is g ++;
Cflags =-wall-O2 specifies the compilation behavior.-O2 indicates that the code optimization is moderate.-G indicates that the code can be debugged, which is equivalent to the debug version in windows, -D and the following parameters indicate that a macro is defined;
Primary des =-I. indicates the directories where the source code is stored,-I. indicates the local directory. If there is a directory of SOC in the directory, this sentence should be written as primary des =-I. -I. /SOC;
Libs =-lpthread indicates that the Connection Library provided by the system is used for connection. multithreading is introduced in the above project. Therefore, the lpthread Connection Library provided by the system must be used;
Objs = thread. O crc32.o ts. O tspacketizer. O utils. O socket. o pdg. O test_pdg.o
Indicates the various. O files to be compiled. If it is the previous example, it should be written as objs = function. O main. O;
Prog = pdgd indicates the name of the target file to be connected, which is the same as that of main.exe;
%. O: %. cpp indicates that the. o file depends on the. cpp file. This is our dependency;
$ (CC) $ (cflags) $ (DES)-C $ <
The above sentence is the statement for compilation. It must be left blank (tab or space) before this sentence, because it is an execution statement. I am not very clear about the details, sorry;
$ (Prog): $ (objs) indicates that the target file depends on the. o file;
$ (CC) $ (libs) $ (objs)-o $ (Prog)
This is a join statement, which must be left blank.

The following clean: and install: are not mandatory. They are available in the MAKEFILE file and are called as tags.

Well, how can I use this file?
1. Write this file and save it to the directory where the source code is located;
2. Run the following command:
# Make
Press enter. Oh, it's very automatic. The compilation and connection we mentioned at the beginning are all done automatically. The above mentioned indicates that there is a mark in the MAKEFILE file, if you only enter make, the statement under the mark is not executed. If you want to execute the marked content, run the following command:
# Make Tag Name
As shown above: # Make clean and # make install.

Depending on the modification time of the code file and the time at which the code file was last compiled, the MAKEFILE file determines the file to be modified and then re-compiled, also, depending on the dependency, the files that are not modified, but the dependent files are modified and need to be re-compiled. Therefore, it is time-saving and labor-saving and worthy of use.

This will be the case for makefile files, and everyone will make progress together. A few days ago, I saw a MAKEFILE file in the system. Wow, it was too complicated. It seems that this MAKEFILE file is also profound and profound, and the path is still long. Please work hard.