Comments in the 9.2 make command and the makefile file 9.2.3 makefile file
comments in the makefile file begin with the # signand continues to the end of this line. As with the C language source file annotations, the annotations in the makefile file can help the writer of the program and others understand the purpose of the original writing of the file.
The macro Mkaefile file in the 9.2.4 Makefile file allows you to write them in a more general format using macros.
defining macros in the Makefile file with statement Macroname=value,
the way to reference a macro is to use $ (MACRONAME) or ${macroname}Some versions of. Make also accept the use of $macroname. If you want to set the value of a macro to NULL, you can leave the equals sign = empty later.
Macros in the makefile file are often used to set the compiler's options. In the software development process, the developers usually do not optimize the results of the compilation, but rather to include debugging information. But for software distributions, they often need to be reversed, That is, the compilation result is a small binary executable that does not contain debugging information, making it perform as fast as possible.
Another problem with the Makefile1 file is that it assumes that the name of the compiler is GCC, and that in other Unix systems, the name of the compiler may be cc or c89. If you want to migrate makefile files to another version of UNIX, or use another compiler on an existing system, To make it work, you will have to modify the contents of many lines in the makefile file. Macros are a great way to collect all of these system-related content, and you can easily modify them by using macro definitions.
Macros are typically defined in the makefile file, or you can give a macro definition on the command line when the make command is called, such as command make cc=c89. The macro definition on the command line overrides the macro definition that will be overwritten in the makefile file. When you use a macro definition outside of the makefile file, Note that the macro definition must be passed as a single parameter, so avoid using spaces in macro definitions or quoting macros.
Write Makefile2, which uses a number of macro definitions
The Make command replaces $ (CC), $ (CFLAGS), and $ (INCLUDE) with the corresponding macro definition, similar to how the C language compiler handles a # define statement.
In fact, the make command has some special macro definitions built into it, which makes the makefile file more concise.
Macro definition
$? The current directory depends on the file list that is newer than the current directory file
[email protected] The name of the current directory
$< the name of the current dependent file
$* the name of the current dependent file that does not include the suffix name
In the makefile file, you may also see the following two useful special characters, which appear before the command.
-: Tell the make command to ignore all errors.
@: Tell make not to display the command on standard output before executing a command. This character is useful if you want to give some explanatory information using the echo command.
9.2. More than 5 targets
It is often useful to make more than one target file or set of commands in a single location, which can be achieved by extending the makefile file. In the following example, add a clean option in the makefile file to delete the unwanted target file Add an install option to mount the successfully compiled application to another directory.
Writing Makefile3
CLEAN:-RM main.o 2.o 3.oinstall:myapp@if [-D $ (instdir)]; Then CP MyApp $ (instdir), chmod a+x $ (instdir)/myapp;chmod og-w $ (instdir)/myapp;echo "installed in $ (instdir)"; else echo " Sorry, $ (instdir) does not exist "; fi
There are several places to note in Makefile3 (as shown above):
First, the special target all still specifies only the MyApp target. Therefore, if you do not specify a target when you execute the Make command, its default behavior is to create a target myapp.
followed by two new targets: clean and install.
Target Clean uses the RM command to delete the target file. The RM command uses the minus-start, minus-sign-meaning of the make command to ignore the execution result of the RM command. This means that even if the RM command returns an error because the destination file does not exist, the command made clean will succeedThe rule used to make the target clean does not define any dependencies on the target clean: The following is empty, so the target is always considered obsolete, so the rule of the target will always be executed if the target clean is specified when executing the making command.
The target install relies on MyApp, so the make command knows that it must first create MyApp before it can execute the other commands required to produce the targetThe rules used to make the install target consist of several shell script commands. Because the make command invokes a shell when executing a rule, and a new shell is used for each rule,
You must add a backslash \ At the end of each line of code above, so that all shell script commands are logically on the same line and passed as a whole to a shell execution. This
The command begins with the symbol @, which indicates that make does not display the command itself on standard output until the rules are executed.
The target installation executes multiple commands sequentially to install the application to its final location. It does not check the success of the previous command before executing the next command. If this is important, you can connect these commands with symbols &&. For example, the CP MyApp ( Instdir) \
&& for the shell, each subsequent command executes only if the previous command succeeds.
Linux programming--make commands and Makefile files (chapter Nineth)
