"Linux" simple makefile and progress bar implementation!! __linux

Compiling a program file in Linux requires the use of gcc/g++, but in a project it may contain more than just a file, so it is time-consuming to compile a single file and increase the risk of a program error. In Linux, you can use make to compile multiple files.
in Linux, in addition to the make instructions, you can compile the files at once, along with the shell script to bring together the operations of multiple ask kin. However, there are several benefits to using make:

* Simplifying the commands that you need to execute
if you modify a source file after the compilation is complete, make only compiles against the modified file and the other target files are not changed
* Finally, you can update the execution file according to dependencies

Give me a chestnut:

MAIN:MAIN.O add.o sub.o mul.o
  2     gcc main.o add.o sub.o mul.o-o main
  3 add.o:add.c
  4 gcc-c add.c-o     A DD.O
  5 sub.o:sub.c
  6     gcc-c sub.c-o sub.o
  7 mul.o:mul.c
  8     gcc-c mul.c-o                                                                       
MUL.O ~< c17/>~                              

The basic syntax and variables of makefile: Basic grammar
Target: Target file 1 target file 2
Gcc-o New executable target file 1 Object 2 The goal is the information we want to build, and the goal is to ask only the relevant object files, and the syntax for the executable file is the one that starts with the key, paying special attention: the command line must be preceded by a key. Basic rules:
The # inside the makefile represents the annotation
Must be the first character on the command line
The target file and related files must be separated by ":"
Example:
ADD.C file:

#include "add.h"
  2  
  3  
  4  
  5 int Add (int a,int b)
  6 {                                                                                               
  7 return     A + b;
  8}
~                                                                                                                                                                                                       

SUB.C file:

#include "Sub.h"
  2  
  3  
  4  
  5 int sub (int a,int b)
  6 {
  7 return     a-b;
  8}                                                                                               
~                                                                                                         

MAIN.C file:

MAIN:MAIN.O add.o sub.o
  3         gcc-o main MAIN.O add.o sub.o
  4 add.o:add.c
  5         gcc-c add.c-o Add.o
  6 SUB.O:SUB.C
  7         gcc-c sub.c-o sub.o
  8 Clean:
  9         rm-rf main.o add.o sub.o

The next step is the makefile content:
Makefile File:

MAIN:MAIN.O add.o sub.o
  3         gcc-o main MAIN.O add.o sub.o
  4 add.o:add.c
  5         gcc-c add.c-o Add.o
  6 SUB.O:SUB.C
  7         gcc-c sub.c-o sub.o
  8 Clean:
  9         rm-rf main.o add.o sub.o

When we execute the make instruction, the result:

After performing a simple makefile, all of the processed files will be placed in the main file.
When executing./main, the result:

Note: The number that appears here is the result of calling function processing in the main function.

But sometimes when you write makefile, you write a lot of instructions, then you can design makefile using the basic syntax of the variable:
For example:
* * * change the above makefile to change

OBJS = main.o add.o sub.o
 LIBS/-lm main:main.o add.o sub.o gcc-o    
       main ${OBJS} ${libs} clean
 :                     
       rm-rf Main ${OBJS}                          

Here, replace MIAN.O ADD.O with Objs SUB.O
ilbs to replace-LM
Results after running the make directive:

Note: This only changes the contents of the main file, so only the main file is updated.
The basic syntax of a variable: the contents of a variable and a variable are separated by "=", while the left side can have a space variable on either side, such as the first row of the example above OBJS the left can not have; The contents of a variable and a variable can be used between "=" and Cannot have ":", in the habit, the variable is preferably "uppercase", using the variable, with the ￥{variable} or ￥ (variable) use, in the shell of the environment variable can be applied, in the command line mode can also define variables;

Because GCC will actively read this environment variable when compiling the behavior, it can define the environment variable directly in the shell.

If this does not do a good job of reducing the amount of code, you can use the command line for input, or you can enter the specified environment variable directly in the file.
For example:

OBJS = main.o add.o sub.o sub.o LIBS =-lm main:main.o add.o sub.o gcc-o $@ ${objs}
     ${libs} clean
:           
     RM -RF $@ ${objs}

The result of calling make:

The $@ here represents the target file, $^ represents the dependent file

The rules of the environment variable are: The environment variable added to the Make command line is the first priority makefile the environment variable within the second priority shell the original environment variable is the third priority

Implementation of simple progress bar
Code:

#include <stdio.h>
#include <unistd.h>
int main ()
{        
    char arr[101] = "#";
    char* r = "\\|/-\\";
    int i = 0;
    for (; i<101;i++)
    {       
        printf ("[%-100s][%c]\r", arr,r[i%6]);
        Arr[i] = ' # ';
        Fflush (stdout);
        Usleep (100000);                                                                                                                                       
    }       
    return 0;

Results: