Linux under make command instance detailed

Linux under Make command instance detailed

The Linux make command is one of the most frequently used commands for system administrators and programmers. Administrators use it to compile and install many open source tools from the command line that programmers use to manage their large and complex project compilation issues. In this article we will use some examples to discuss the working mechanism behind the make command.

How make is working

For those who do not know the underlying mechanism, the make command receives the target as if it were a command line parameter. These goals are usually stored in a special file named "Makefile", and the file also contains actions that correspond to the target. For more information, read a series of articles on how makefiles works. Server Tutorials

When the make command is executed for the first time, it scans the Makefile to find the target and its dependencies. If these dependencies themselves are targets, continue to establish their dependencies for these dependency-scan Makefile and compile them. Once the master relies on compilation, the main target is compiled (this is passed in by the Make command).

Now, if you modify a source file and you execute the make command again, it will only compile the target file associated with the source file, so it saves a lot of time to compile the final executable.

Make command instance

The following is the test environment used in this article:

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Os--ubunut 13.04 shell--bash 4.2.45 application--gnu make 3.81

Here is the project's content:

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1 2	$ ls anothertest.c Makefile test.c test.h

Here's what the Makefile:

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All:test test:test.o anothertest.o gcc-wall test.o anothertest.o-o test test.o:test.c gcc-c-Wall test.c anoth ertest.o:anothertest.c gcc-c-wall anothertest.c clean:rm-rf *.o test

Now let's look at some examples of the application of the Make command in Linux:

1. A simple example

In order to compile the entire project, you can simply use make or take the target all after the makes command.

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$ make gcc-c-wall test.c gcc-c-wall anothertest.c gcc-wall test.o anothertest.o-o test

You can see the dependencies that the make command created for the first time and the actual target.

If you look at the contents again, there are a few more. o Files and execution files:

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1 2	$ ls anothertest.c anothertest.o Makefile test test.c test.h TEST.O

Now, let's say you made some changes to the test.c file and reuse the make compilation project:

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$ make gcc-c-wall test.c gcc-wall test.o anothertest.o-o test

You can see that only TEST.O has been recompiled, yet another TEST.O has not been recompiled.

Now clear all the target files and executable file test, you can use target clean:

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$ make clean rm-rf *.o test $ ls anothertest.c Makefile test.c test.h

You can see all of the. o files and the execution file test are deleted.

2. Use the-B option to always re-establish all goals

So far, you may have noticed that the make command does not compile files that have not changed since the last compilation, but you can use the-B option if you want to override the default behavior of making.

Here's an example:

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$ make make:nothing to is done as ' all '. $ make-b gcc-c-wall test.c gcc-c-wall anothertest.c gcc-wall test.o anothertest.o-o test

You can see that although the make command does not compile any files, Make-b forces the compilation of all the target files and the final execution files.

3. Print debugging information using the-D option

If you want to know what you actually did with make execution, use the-D option.

This is an example:

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$ make-d | more GNU make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; The source for copying conditions. There is NO warranty; Not even for merchantability or FITNESS for A particular purpose.   This program built for X86_64-pc-linux-gnu Reading makefiles ... Reading makefile ' makefile ' ... Updating makefiles ..... Considering target file ' Makefile '. Looking for a implicit rule for ' Makefile '. Trying pattern rule with stem ' Makefile '. Trying implicit prerequisite ' makefile.o '. Trying pattern rule with stem ' Makefile '. Trying implicit prerequisite ' makefile.c '. Trying pattern rule with stem ' Makefile '. Trying implicit prerequisite ' makefile.cc '. Trying pattern rule with stem ' Makefile '. Trying implicit prerequisite ' makefile.c '. Trying pattern rule with stem ' Makefile '. Trying implicit prerequisite ' Makefile.cpp '. Trying pattern rule with stem ' Makefile '.  --more--

This is a very long output and you also see that I used the more command to show the output on a page.

4. Use the-C option to change the directory

You can provide a different directory path for make commands and switch directories before looking for Makefile.

This is a directory, assuming you are in the current directory:

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$ ls file file2 frnd frnd1.cpp log1.txt log3.txt log5.txt file1 file name with spaces Frnd1 Frnd.cpp log2.txt log4.txt

But the Makefile file for the make command you want to run is saved in the. /make-dir/directory, you can do this:

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$ make-c. /make-dir/make:entering directory '/home/himanshu/practice/make-dir ' make:nothing to being done as ' all '. Make:leaving directory '/home/himanshu/practice/make-dir

You can see that the make command first cuts to a specific directory, executes there, and then switches back.

5. View other files as Makefile with the-f option

If you want to rename a Makefile file, such as a my_makefile or some other name, we want make to use it as a Makefile, and the-f option can be used.

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1	Make-f My_makefile

In this way, the make command chooses to scan my_makefile instead of makefile.