Lspci detailed analysis using, PCI device tree

Lspci detailed analysis using, PCI device tree I. INTRODUCTION of PCI PCI is a peripheral bus specification. Let's take a look at what a bus is: A bus is a path or channel for transmitting signals. Typically, the bus is an electrical connection to one or more conductors, and all the devices connected on the bus can receive all the transmitted content at the same time. The bus consists of an electrical interface and a programming interface. This article discusses the device drivers under Linux, so focus on programming interfaces. PCI is the abbreviation for peripheral Component Interconnect (peripheral interconnect) and is commonly used as a peripheral bus on desktops and larger computers. The PCI architecture is designed as a replacement for the ISA standard, with three main goals: better performance when transferring data between computers and peripherals, as platform-agnostic as possible, and simplifying the task of adding and removing peripherals to the system. Second, PCI addressing From now on, I want to try to illustrate the problem as much as possible through practical examples, while reducing the theoretical aspects of the problem, because, the relevant theory of things can be found elsewhere. Let's take a look at an example where the physical memory address space of my computer with a 1G ram,1g is a mapping of the external device IO on the system memory address space. /proc/iomem describes the mapping of all device I/O in the system to the memory address space. Let's see how the first device with the address starting with 1G is described in/proc/iomem: 40000000-400003ff:0000:00:1f.1 This is a PCI device, 40000000-400003FF is its mapped memory address space, occupies the memory address space of the bytes location, and 0000:00:1F.1 is a PCI peripheral address, which is separated by a colon and a comma 4 parts, The first 16-bit represents the domain, the second 8-bit represents a bus number, the third 5-bit represents a device number, and finally 3-bit, which represents the function number. Because the PCI specification allows a single system to have up to 256 buses, the bus number is 8 bits. However, for large systems, this is not enough, so, introduced the concept of the domain, each PCI domain can have up to 256 bus, each bus can support 32 devices, so the device number is 5 bits, and each device can have up to 8 functions, so the function number is 3 bits. Thus, we can conclude that the address of the above PCI device is the number 1th function on the No. 31st device on the No. No. 0 field No. 0 bus. What exactly is this PCI device above? Here is the output of the LSPCI command on my computer: 00:00.0 host Bridge:intel Corporation 82845 845 (Brookdale) Chipset Host Bridge (Rev. 04) 00:01.0 PCI Bridge:intel Corporation 82845 845 (Brookdale) Chipset AGP Bridge (Rev. 04) 00:1d.0 USB Controller:intel Corporation 82801ca/cam USB (Hub #1) (rev. 02) 00:1d.1 USB Controller:intel Corporation 82801ca/cam USB (Hub #2) (rev. 02) 00:1e.0 PCI Bridge:intel Corporation 82801 Mobile PCI bridge (Rev. 42) 00:1f.0 Isa Bridge:intel Corporation 82801CAM Isa Bridge (LPC) (rev 02) 00:1F.1 IDE Interface:intel Corporation 82801CAM IDE U100 (rev 02) 00:1F.3 Smbus:intel Corporation 82801ca/cam SMBus Controller (rev. 02) 00:1F.5 Multimedia Audio Controller:intel Corporation 82801ca/cam AC ' Audio Controller (rev 02) 00:1F.6 Modem:intel Corporation 82801ca/cam AC ' 02 Modem Controller 01:00.0 VGA compatible Controller:nvidia Corporation NV17 [GeForce4 420 Go] (rev A3) 02:00.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (Rev. 46) 02:01.0 Ethernet Controller:realtek Semiconductor Co., Ltd. rtl-8139/8139c/8139c+ (Rev 10) 02:04.0 CardBus Bridge:o2 Micro, Inc. OZ6933 CardBus Controller (rev. 01) 02:04.1 CardBus Bridge:o2 Micro, Inc. OZ6933 CardBus Controller (rev. 01) LSPCI does not indicate a domain, but for a PC, there is typically only one domain, or domain No. 0. With this output we can see that it is an IDE interface. As can be seen from the above output, there are 3 PCI buses on my Computer (number No. 0, number 1th, 2nd). On a single system, inserting multiple buses is done through a bridge (bridge), which is a special PCI peripheral used to connect the bus. So, the overall layout of the PCI system is tree-shaped, and we can draw the tree structure of the PCI system on my computer through the LSPCI output above: 00:00.0 (main bridge)--00:01.0 (PCI bridge)-----01:00:0 (NVIDIA graphics card) | |---00:1d (USB controller)--00:1d:0 (USB1 Controller) | | | |--00:1d:1 (USB2 Controller) | |-00:1e:0 (PCI bridge)--02:00.0 (IEEE1394) | | | |-02:01.0 (8139 network card) | | | |-02:04 (CardBus bridge) -02:04.0 (bridge 1) | | | |--02:04.1 (Bridge 2) | |-00:1F (multifunction Board) -00:1f:0 (ISA bridge) | |--00:1f:1 (IDE interface) | |--00:1f:3 (SMBus) | |--00:1f:5 (multimedia sound Controller) | |--00:1f:6 (Modem) From the figure above, there are 8 PCI devices on my computer, of which there are 4 on bus No. 0 (main bridge) and 1 on bus 1th and 2nd on bus 3. The 00:1f is a multi-function board with 5 functions. It is easy to understand that each PCI device has its mapped memory address space and its I/O area. In addition, the PCI device also has its configuration register. With the configuration register, the PCI driver does not need to be probed to access the device. The layout of the configuration register is standardized, and the 4 bytes of the configuration space contain a unique feature ID, so the driver can identify its device by querying the specific ID of the peripheral. Therefore, the main innovation of the PCI interface standard above ISA is to configure the address space. As already mentioned, the PCI driver does not require probing to access the device, which is due to the configuration of the address space. During the system boot phase, the PCI hardware device remains inactive, but each PCI motherboard is equipped with firmware capable of handling PCI, and the firmware provides access to the device configuration address space by reading and writing the registers in the PCI controller. The first 64 bytes of the configured address space are standardized, providing information such as vendor number, device number, version number, and uniquely identifying a PCI device. It also provides up to 6 I/O address areas, each of which can be memory or I/O addresses. These several I/O address areas are the only way that the driver finds the exact location of the device mapping to memory and I/O space. With these two points, the PCI driver completes the function equivalent to probing. For details on this 64-byte configuration space, refer to the third version of the Linux device driver P306, which is no longer detailed. Let's look at the details of the configuration space for the 8139too NIC device. In the 2.6 kernel system, you can see many directories named after the PCI device name under directory/sys/bus/pci/drivers/, but not all of these devices are present in your system. We entered the 8139too directory, which has a directory named after its device address 0000:02:01.0. In this directory you can find a lot of information about this network card device. where resource records its 6 I/O address areas. The contents are as follows: 0x0000000000003400 0x00000000000034ff 0x0000000000000101 0x00000000e0000800 0x00000000e00008ff 0x0000000000000200 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 As can be seen from this file, the 8139too device uses two I/O address areas, the first is the I/O port range It maps, and the second is the memory address space it maps. About these two values can be verified in/proc/iomem and/proc/ioport. -[0000:00]-+-00.0 +-02.0 +-1d.0 +-1d.1 +-1d.2 +-1d.7 +-1e.0-[0000:01]--+-02.0 | \-05.0 +-1f.0 +-1f.1 +-1f.3 \-1f.5 00:00.0 Host bridge:intel Corporation 82845g/gl[brookdale-g]/ge/pe DRAM controller/host-hub Interface (rev. 03) 00:02.0 VGA compatible Controller:intel Corporation 82845g/gl[brookdale-g]/ge Chipset Integrated Graphics Device (rev. 03) 00:1d.0 USB Controller:intel Corporation 82801db/dbl/dbm (ich4/ich4-l/ich4-m) USB UHCI Controller #1 (rev 02) 00:1d.1 USB Controller:intel Corporation 82801db/dbl/dbm (ich4/ich4-l/ich4-m) USB UHCI Controller #2 (rev 02) 00:1d.2 USB Controller:intel Corporation 82801db/dbl/dbm (ich4/ich4-l/ich4-m) USB UHCI Controller #3 (rev 02) 00:1d.7 USB Controller:intel Corporation 82801db/dbm (ich4/ich4-m) USB2 EHCI Controller (rev 02) 00:1e.0 PCI Bridge:intel Corporation 82801 PCI bridge (Rev. 82) 00:1f.0 ISA Bridge:intel Corporation 82801db/dbl (ich4/ich4-l) LPC Interface Bridge (rev. 02) (LPC Hub Controller 1) 00:1F.1 IDE Interface:intel Corporation 82801DB (ICH4) IDE Controller (rev. 02) 00:1F.3 Smbus:intel Corporation 82801db/dbl/dbm (ich4/ich4-l/ich4-m) SMBus Controller (rev. 02) 00:1F.5 Multimedia Audio Controller:intel Corporation 82801db/dbl/dbm (ich4/ich4-l/ich4-m) AC ' Audio Controller (rev 02 ) 01:02.0 communication controller:conexant HSF 56k HSFI Modem (rev 01) 01:05.0 Ethernet Controller:realtek Semiconductor Co., Ltd. rtl-8139/8139c/8139c+ (Rev 10) http://apps.hi.baidu.com/share/detail/18492464