Make tools and Makefile files

Make tools and Makefile files

Read Catalogue

• 1. Make tool
• 2. Makefile File
• 3. Simple example of makefile
• 4. Pseudo-target
• 5. Makefile Automation variables
• 6. Compile and build more than one executable file
• 7. Make common inline functions

Body

Back to top of 1. Make Tools

The Make tool allows you to automate the compilation process, including:

• If you modify a few source files, only the several source files are recompiled
• If a header file is modified, all source files containing the header file are recompiled

This automatic compilation can greatly simplify the development effort and avoid unnecessary recompilation. The Make tool completes and automatically maintains the compilation through a file called Makefile, and the makefile file describes the compilation and connection rules for the entire project.

Back to top of 2. Makefile file

Makefile describes the compilation connection rules for the entire project. The basic rules of Makefile are:

TARGET...: DEPENDENCIES...    COMMAND    ...

• Targer: Files generated by the target program, such as executables and target files, can also be actions to be performed, such as clean, also known as pseudo-targets.
• DEPENDENCIES: Dependency is a list of input files used to produce a target, and a target is usually dependent on multiple files.
• Command: Commands are actions performed by make (commands are shell commands or programs that can be executed under the shell), and note that the starting character of each command line must be the tab character.
• If one or more files are updated in dependencies, the command is executed, which is the core content of makefile.

Back to top of 3. A simple example of makefile

$ touch add.c add.h sub.c sub.h main.c

Now there are 5 files Add.h, Sub.h contains the function declaration, ADD.C, SUB.C contains the function implementation, MAIN.C called the function. Makefile Files:

Main: MAIN.OAdd. oSubThe. O "target file isMain, which relies onMain. O,Add. O,Sub. o These three documents "Gcc-wall-GMain. oAdd. oSub. o-OMain "command to be executed by dependent file generation target file"Main. o: MAIN.CGcc-wall-G-CMain. C-OMain. oAdd. o: ADD.CAdd. hGCC -wall -g Span class= "Hljs-selector-tag" >-c add.c -o add.osub.o:SUB.C sub.h GCC -wall -g -c sub.c -o sub.o        

After saving the makefile file, execute the Make command:

$ makegcc -Wall -g -c main.c -o main.ogcc -Wall -g -c add.c -o add.ogcc -Wall -g -c sub.c -o sub.ogcc -Wall -g main.o add.o sub.o -o main

You can see that after make is executed, because the target file main relies on MAIN.O ADD.O SUB.O, it is necessary for Mr. to become these three. o files, and finally generate main.
If you enter make again at this point, you will see:

makemake: ‘main‘ is up to date.

The compilation rules for make are judged by time , and once a file in the dependency list is updated later than the target file, the target will be rebuilt, or the above hint will appear.
By default, tapping make will generate the first target, which is main. You can also generate a specified target:

make add.o   【指定只生成add.o文件】

The name of the Makefile file is not necessarily named "Makefile" or "Makefile", and it is also possible to use other names. For example we are called Mymakefile by a file and can also use it:

-f myMakefile   【-f 选项的作用是把名字"myMakefile"作为makefile来对待。】

Back to top of 4. Pseudo target

TARGET...: DEPENDENCIES...    COMMAND    【注意COMMAND之前是一个TAB，不是空格】 ...

As I said earlier, target can be a pseudo-target in addition to being a target file. The effect of executing a pseudo-target is equal to performing an action and does not produce a target file. For example, add a pseudo-target:

main:main.o add.o sub.o             gcc -Wall -g main.o add.o sub.o -o main  main.o:main.c        gcc -Wall -g -c main.c -o main.oadd.o:add.c add.h gcc -Wall -g -c add.c -o add.osub.o:sub.c sub.h gcc -Wall -g -c sub.c -o sub.oclean : 【这是一个伪目标】 rm -f $(OBJECTS) main 

Use make to perform pseudo-targets:

sub.o main  

You can see that make will execute the command below the pseudo target.

Back to top of 5. Makefile Automation variables

From the makefile file above we find some problems: Sometimes the dependency list of the target file is too long, or the command repeats. This problem can be solved by using makefile automation variables.

Option Name	function
[Email protected]	The target file name of the rule
$<	The first dependent file name of a rule
$^	List of all dependent files for the rule

Just now the makefile file that we can rewrite as:

main:main.o add.o sub.o        gcc -Wall -g $^ -o [email protected]      【等价于 gcc -Wall -g main.o add.o sub.o -o main】main.o:main.c        gcc -Wall -g -c $< -o [email protected]add.o:add.c add.h gcc -Wall -g -c $< -o [email protected]sub.o:sub.c sub.h gcc -Wall -g -c $< -o [email protected]

Perform make to see that the effect is the same as before:

$ makegcc -Wall -g -c main.c -o main.ogcc -Wall -g -c add.c -o add.ogcc -Wall -g -c sub.c -o sub.ogcc -Wall -g main.o add.o sub.o -o main

You can also customize variables :

OBJECTS = main.o add .o sub.o 【OBJECTS是自定义的变量名】main:$(OBJECTS)                        【可以在需要的地方使用变量名进行替换，替换规则为$(变量名)】 gcc -Wall -g $^ -o [email protected]main.o:main.c gcc -Wall -g -c $< -o [email protected]add.o:add.c add.h gcc -Wall -g -c $< -o [email protected]sub.o:sub.c sub.h gcc -Wall -g -c $< -o [email protected]

Back to top of 6. Compile to build multiple executables

Suppose now not just want to build executable main, also want to build executable file main2, can write like this

BIN = main main2                【自定义变量BIN】OBJECTS= main.o add.o sub.o  : $(BIN)   【关注重点】main : $(OBJECTS)        gcc -Wall -g  $< -o [email protected]main2: $(OBJECTS)        gcc -Wall -g  $< -o [email protected]main.o : main.c        gcc -Wall -g -c $< -o [email protected]main2.o :msin2.c gcc -Wall -g -c $< -o [email protected]add.o:add.c add.h gcc -Wall -g -c $< -o [email protected]sub.o:sub.c sub.h gcc -Wall -g -c $< -o [email protected]clean : rm -f $(OBJECTS) $(BIN)

In order to generate the target file all, you need to be Mr. Bin, which is the main main2. This allows the creation of two executables. With custom variables, you can simplify this makefile file again:

: $(BIN)main : $(OBJECTS)        $(CC) $(CFALGS)  $< -o [email protected]main2: $(OBJECTS)        $(CC) $(CFALGS)  $< -o [email protected]       main.o : main.c        $(CC) $(CFALGS) -c  $< -o [email protected]main2.o :msin2.c $(CC) $(CFALGS) -c $< -o [email protected]add.o:add.c add.h $(CC) $(CFALGS) -c $< -o [email protected]sub.o:sub.c sub.h $(CC) $(CFALGS) -c $< -o [email protected]clean : rm -f $(OBJECTS) $(BIN)

But this seems to be more repetitive, and you can use the following method to continue simplifying:

BIN = Main Main2objects= MAIN.O ADD.O SUB.OCC = gccCfalgs =-Wall-gall:$(BIN) Main:$(OBJECTS)$ (cc) $ ( CFALGS) $<-o [email protected]main2: $ (objects) $ (CC) $ (cfalgs) $<-O [email protected]. O C: "Focus here" $ ( cc) $ (cfalgs)-C $<-o [email protected]clean:rm-f $ (objects) $ (BIN)   

Using the. O.C:, you can automatically generate all the. c files to the. o file using the same command to complete, simplifying repetitive work.

Back to top of 7. Make common inline functions

First look at the form of function calls in Make:

//函数调用$(function arguments)     【function是函数名称，arguments是参数，使用$来调用】

It is important to note that there is a space between the function name and the parameter.

Let's look at three common make inline functions.

• The $ (wildcard pattern) function is a file that matches the pattern in the current directory.

$(wildcard *.c)  【在当前目录下搜索所有.c文件，文件名称列表保存到src中】

• $ (Patsubst pattenr,replacement,text) mode substitution function, which replaces the file list in TEXT with the replacement mode from the schema Pattenr.

$(patsubst %.c,%.o,$src)  【把src中的.c文件列表中的文件从.c替换为.o】等价于：$(src:.c =.o)   【这种方式更常用】

• Shell functions

Shell functions can execute commands under the shell, as well as using $ to reference, for example

$(shell ls -d */) 【将当前目录下的所有文件夹都列出来】

The following is an example of a multilevel directory that uses these functions. The scenario is that the current directory has a main.c file, and there are several directories, each with its own. c file. Generate the final main file using all of the. c File Compilations:

CC = gccCFLAGS =-Wall-gBIN = MainSubDir =$ (Shell ls-d */) "The subdir variable holds a list of subdirectories "ROOTSRC =$ (wildcard *.c) "ROOTSRC saves the list of. c files in the current directory.Rootobj =$(ROOTSRC:%.C =%.O) "Rootboj saves the. O list with the same name as the. c file under the current directory.SUBSRC =$ (Shell find$(SubDir)-name' *.c ') "Subsrc Save the. c File under all subdirectoriesSubobj =$(SUBSRC:%.C =%.O) "Subobj saves the. o file list with the same name as the. c file under all subdirectories.$(BIN):$(rootobj) $ (subobj) "The build of main depends on the. o file under the current directory and all subdirectories" $ (cc) $ ( CFLAGS)-O $ (bin) $ ( rootobj) $ (subobj). O. C: $ ( cc) $ (cflags)-C $<-o [email protected] clean:rm-f $ (bin) $ (ROOTOBJ) $ (subobj)          

Article Link: http://www.cnblogs.com/QG-whz/p/5461110.html

Make tools and Makefile files