Makefile Brief Introduction

　　Now the IDE environment is mostly highly integrated, only need to press a button to complete the compilation-assembly-link work, but in the process of embedded development, need to write according to the actual needs of the individual needs, which need to master the makefile.

　　The convenience of the advanced IDE is based on makefile, and makefile is actually a script file that tells the compiler to rely on the file and the compilation rules, which is similar to the batch file under Windows.

　　A makefile consists of a number of program segments, each with a set of commands to complete the work. The program section is distinguished by the target name, which is also known as the label. When different program degrees need to be associated, you can have one or more labels associated with the program segment after the target, separated by a space between each associated label, and in the command set, the command line must start with the TAB key, such as the following format:

　　Program Label: Associated program segment target 1 associated program segment target 2

Command set

There is an appropriate metaphor in Ren Zhe's book to illustrate how makefile is executed:

　　Sweet and sour pork ribs: sweet and sour pork

Making sweet and sour pork ribs

Sugar:

Go to the store to buy sugar

Vinegar:

Go to the store to buy vinegar

Ribs:

Go to the store and buy ribs.

in fact, if you execute this makefile with the Make command, the first paragraph is executed by default, but if the target file is not ready, look for the program segment that generated the target file. In addition, when writing makefile, it is best to write all dependencies, so that the table is clear and neatly formatted. 　　 In addition, there is a makefile program segment is a bit special, this is pseudo-target, pseudo-target in short is to generate the final target has no effect on target, such as the elimination of the project compiler automatically generated some files.

Makefile can also define variables, use "Variable name = value" To declare a variable, you can refer to this variable by using the $ (variable name) to reference.

Comments in makefile use #, if the dependent file is long, you can use the ' \ ' for a career change function.

Makefile Brief Introduction