Makefile General wording

I. Role of Makefile

Makefile is used for automatic compilation and linking, a project has a lot of file composition, each file changes will cause the project to relink, but not all the files need to recompile, makefile recorded in the file information, make determines which files need to be recompiled when linking. Makefile's mission is to let the compiler know which files to build a file to rely on. When those dependent files are changed, the compiler automatically discovers that the final makefile is obsolete and should recompile the corresponding module. Makefile brings the benefit is-"automated compilation", once written, only need a make command, the entire project completely automatic compilation, greatly improve the efficiency of software development. By default, the make command searches the current directory for files named "Gnumakefile," "Makefile," and "Makefile," and finds an explanation for the file. Of course, you can use Make-f dir/makefile to specify the makefile file

two. Several basic knowledge of Makefile 1. The difference between assignment symbols
= is the most basic assignment, which is only assigned after use, and cannot be appended after the variable
: = is the value before overwriting, immediate assignment, you can append the content after the variable
? = is the value that is given after the equal sign if it has not been assigned
+ = is the value after the equals sign is added
2. Automatic variable $< The name of the first dependent file
$? All dependent files, separated by spaces, are modified to date later than the target creation date
$@ the full name of the target
$^ all dependent files, separated by spaces, does not contain duplicate dependent files

3. Several commonly used functions 1. $ (patsubst%.c,%.o,x.c.c bar.c)
Replace the word "x.c.cbar.c" with the pattern [%.c] with [%.O], returning the result is "X.C.OBAR.O"
2.$ (Filter <pattern...>,<text>)
Filters the words in <text> strings in <pattern> mode, preserving the words that conform to the mode <pattern>. Can have more than one pattern.
3.$ (Filter-out <pattern...>,<text>)
4.$ (foreach <var>,<list>,<text>)
Take out the words in the parameter <list> and put them in the variable specified by the parameter <var>, and then execute the expression contained in <text>. Each time <text> returns a string that loops through the process.
5.shell functions, such as files: = $ (shell echo *.c)

three. The compilation process of the Universal Makefile begins recursively into subdirectories from the top level, and when it goes to the bottom of a directory, it starts using compiler compilation, Then pack all the. o files for the layer into BUILD-IN.O, returns its upper level directory and recursively enters the subdirectory, and when all subdirectories are compiled, the top-level. c file is compiled and the top-level. o file and the build-in.o of each subdirectory in the top level are linked to our target file.

Mind Mapping:

four, the actual combat

If there is such a directory structure of the project

A

----D

----A.C

B

----B.C

C

----C.C

Main.c

Top Makefile: [Plain]  View Plain  copy cross_compile =   as      = $ (CROSS_ COMPILE) as   ld      = $ (cross_compile) ld   CC       = $ (cross_compile) gcc   cpp     = $ ( CC)  -E   ar      = $ (cross_compile) ar   nm       = $ (cross_compile) nm      strip        = $ (cross_compile) strip   objcopy     = $ (CROSS_ COMPILE) objcopy   objdump     = $ (cross_compile) OBJDUMP      export as ld cc cpp ar nm   export strip objcopy  OBJDUMP      cflags := -wall -o2 -g      ldflags  :=       export cflags ldflags      topdir := $ ( SHELL&NBSP;PWD)    export topdir      target := test          obj-y += main.o    obj-y += a/    obj-y += b/    obj-y += c/      all :         make -c ./ -f $ (Topdir)/makefile.build       $ (CC)  $ (ldflags)  -o $ (TARGET)  built-in.o         clean:       rm -f $ (shell find -name  "*.O")        rm -f $ (shell find -name  "*.D")         rm -f $ (TARGET)   . phony:all clean   
here is the definition of a number of variables, all is the project default goal, it is a pseudo target, into the pseudo target after the execution of the command is to execute makefile.build, here will cause a recursive call, Makefile.build is also invoked in the Makefile.build. Until Makefile.build returns, the final target file is generated using the BUILT-IN.O generated by Makefile.build.

Makefile.build:

[plain] view plain copy phony: = Build build:obj-y: = subdir-y: =