Makefile Learning under Linux

[What is make?] ]

　Make is a command tool that is a command tool that interprets instructions in makefile. It simplifies the instructions that are placed in the compilation process, and when make is executed, makes searches the current directory for the Makefile (or Makefile) text file and performs the corresponding operation. Make will automatically determine whether the original code has been changed, and automatically update the execution file.

[Why use make?] ]

　　Suppose, now that a project contains 100 program files, if you want to compile this project, then there are 100 compiler instructions. If you want to recompile, then you have to do it again as before. This repetitive and tedious work is really upsetting to us. So, is it convenient to call GCC indirectly by making the operation? If we have changed some of the original code files, then make can also proactively determine which source code and the relevant target file has been updated, and only update the file. This can reduce the time it takes to recompile, and it is more convenient.

[What is makefile again?] ]

makefile is actually a document, which defines a series of rules that specify which files need to be compiled first, which files need to be compiled, which files need to be recompiled, and it records the details of how the original code was compiled! Makefile once written, only need a make command, the entire project is automatically compiled, greatly improving the efficiency of software development.

[definition]

The makefile file consists of a series of rules . The form of each rule is as follows.

<target>: <prerequisites>
[Tab] <commands>

Above the first line of the colon before the section, called "Target", the part after the colon is called "preconditions" (prerequisites), the second line must be a tab key, followed by "command" (commands).

Goal:

One goal is to form a rule. The target is usually the file name, indicating the object to be built by the make command, which can be a file name or multiple file names. separated by a space.

In addition to the file name, the target can also be the name of an operation (for example, clean), which is called a "pseudo-target" (phony targets)

Pre-conditions:

A precondition is usually a set of filenames, separated by a space. It specifies the criteria for whether the "target" is rebuilt: as long as a pre-file does not exist or has been updated (the last-modification timestamp of the predecessor file is newer than the timestamp of the target), the "target" needs to be rebuilt.

Command:

The command (commands) indicates how the target file is updated, consisting of one or more lines of shell commands. It is a specific instruction to build a "target", which usually results in the creation of a target file.

When you write down a rule, for example:

UNIT:OUTPUT.O test2.o     -O Unit OUTPUT.O TEST2.O

That is, let the compiler use (OUTPUT.O test2.o) as a precondition, using the GCC compiler to chain these two target files into a unit executable file,

However, if one of the two files (OUTPUT.O test2.o) does not exist, we can add two rules to the makefile file to generate the file.

output.o:test2.h output.c     -C output.ctest2.o:test2.h    test2.c-C test2.c

For a header file of two source files, use a complete makefile file to specify the compilation rules between them:

UNIT:OUTPUT.O test2.o     -o unit output.o test2.ooutput.o:test2.h output.c    -C output.ctest2.o:test2.h    test2.c-C TEST2.C#删除所有目标文件 and declares that clean is a pseudo-target. Phony:cleanclean:    *.O

Execution Result:

Make the process of working with makefile files a bit more?

By default, make starts at the first target, which is called the default final target . The unit in the makefile file above.

Thus, when we knock the make command at the terminal, make reads the makefile file in the current directory and begins to process the first rule, in this case the link is delivered to the unit executable file,

However, before make can complete this rule work, the obj files relied on by the unit must be processed, and the obj files are processed and updated according to their own rules, and the update rule for each obj file is to compile its source files. If the source file does not change, it is not recompiled.

The processing of other rules is judged by their dependencies on the target and the default final goal, and will not be executed if there are no associations. Unless you tell make to enforce. For example: [Make clean]

After the obj file has been recompiled (if necessary), make decides whether to re-link the executable to the unit. If any file changes, compile the dependent files and generate a new executable file.

Resources:

Https://www.cnblogs.com/qiaopei/p/5550168.html

Makefile Learning under Linux