Makefile Note: Working Principle of makefile and Application of implicit rules

It starts with a single-stage makefile with only one makefile.

For a slightly larger project or software, the source program (. c file or. H files), as well as the source program folder, is definitely not just a file or source program folder, think about when your code is only one source program or program folder. A good programmer always wants to write code files clearly and clearly. The functions of the program can be roughly seen through different folders without names.

When there is only one source program file, such as main. h, Main. c. At this time, due to the small number of source program files, we can manually compile the program: GCC main. c-o main_exe. At this time, it is very convenient to manually compile the program. However, if there are dozens or even hundreds of thousands of programs, it is difficult to manually compile the source program through GCC. In addition, good programmers will consider the relationship between program portability and program files. We always want to take the source program and compile it directly before it can run, we will place the source program in different folders. In this way, it is more difficult to manually compile the program. At this time, the advantages of makefile are apparent.

The following example shows how to write makefile,

 

 

/*

*************************************

Name: example-one.c

*************************************

*/

# Include example-one.h"

{

.......

........

}

 

 

*************************************

Name: example-one.h

Every. C source program has a. h with the same name.

Make some declarations accordingly.

*************************************

*/

# Include <>

# Include <>

 

 

 

 

/*

*************************************

Name: example-two.c

*************************************

*/

# Include example-two.h"

# Include example-one.h"

{

.......

........

}

 

 

*************************************

Name: example-two.h

Every. C source program has a. h with the same name.

Make some declarations accordingly.

*************************************

*/

# Include <>

# Include <>

 

 

 

 

 

.....

.....

 

 

*************************************

Name: Main. c

*************************************

# Include example-two.h"

{

}

 

Here I will not talk about makefile rules. For these rules, the compilation of makefile on the internet is similar. I will mainly talk about the working principle of makefile.

According to the relationship between the above files is not difficult to see, example-two.c because of the use of example-one.c, so when we compile the example-two.c needs example-one.c.

Let's talk about several keywords first.

Target: cond

According to the makefile rules, target is the target, and cond is the condition required to compile the target.

In fact, in many cases, our makefile can only be written

%: %. O

This rule is fine.

Take this example. Although according to the actual situation, there is a hierarchical relationship, Main. O compilation requires example-two.c, example-two.h as necessary conditions, likewise, example-two.o needs example-one.h and example-one.c as necessary conditions.

However, you can try to simplify the makefile in this example:

Objs: = Main. O example-one.o example-two.o

Exec: = test

$ (EXEC): $ (objs)

Tab gcc-o $ (EXEC) $ (objs)

 

After writing commamd, make can compile the program. It is absolutely no problem.

Makefile is also a script language. He only needs to know which target file objs is required to compile the exec Program (here for the target file. o file, source file. H ,. c files with the same name are very important, so it is very convenient to develop this habit ).

The execution steps for GNU make are as follows:

1. Read all makefiles.

2. Read Other makefiles to be included.

3. initialize the variables in the file.

4. Deduce hidden rules and analyze all rules.

5. create dependency links for all target files.

6. Determine the targets to be regenerated Based on the dependency.

7. Run the generated command.

When make knows the target file required by the executable file. after the o file, he finds out what is required to generate the executable file. o file, it will be searched in the current directory you specified, when he cannot find. o file, it will start implicit rules to try to generate. o file. Similarly, when the. o file is generated, the corresponding. c file and. h file will be searched. This is the real reason for the simple makefile in this example. While the makefile compilation work is finally implemented to give the file, let make find the file. The source program itself. the include in the C file also tells makefile ,. what are the requirements for C files. h condition, so in. c file. O files can be automatically completed during the process, and we do not need to explicitly tell them these relationships.

To give an inappropriate analogy:. C. h is equivalent to a person. After make, The. o file of the family is formed by using the # include relation such as extern.

Family. O: Zhang. c Wang. c zhang_son.h

All people use this relationship to form a family.

Then, executable files such as the community are composed of. O files such as families. In this phase, only the families in the community need to be listed, and the Community is automatically formed.

Community: family_one.o family_two.o...

In short, all the. O files required are listed in the rules for assembling executable programs.

 

 

 

 

 

 

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