Makefile of the Linux drive series

Embedded in the Linux environment, whether it is writing applications or drivers, and so on, need to use make to compile the program, you need to learn to write makefile. A simple makefile file is as follows:

1 hell:hello.c 2     gcc-o hello hello.c3clean:4     rm-f Hello

This is the simplest makefile,makefile function that a writer can decide which files need to be compiled. The 2, 4 lines above need to use the TAB key to not use spaces.

You can define variables and use functions in makefile.

Variables defined in makefile:

In Makefile, a variable is a name (like a macro in the C language) that represents a text string (the value of a variable). Where a variable is referenced in the target, dependency, and command of Makefile, the variable is replaced by its value (the same way as the macro reference in C), so other versions of make also refer to variables as "macros". variable names are case-sensitive. The variables "foo", "foo", and "Foo" refer to three different variables. Makefile traditional practice is that variable names are all capitalized.

A reference to a variable: once we have defined a variable, we can use it in many places in the Makefile. A variable is referenced by "$ (variable_name)" or "${variable_name}" to refer to the definition of a variable . a reference to a variable can be in any context of Makefile, the target, the dependency, the command, the vast majority of indicators, and the assignment of a new variable. Here is an example where the variable objects holds a list of all. o Files:

objects = PROGRAM.O foo.o UTILS.O
Program: $ (objects)
Cc-o Program $ (objects)

$ (objects): Defs.h

In GNU make, variables are defined in two ways (or styles). We can think of variables defined in these two ways as two different styles of variables. The difference between these two different styles of variables is: 1. the way of definition; 2. Expand the timing.
1. Recursive expansion variables
The definition of this type of variable is defined by "=" or by using the indicator "define". The reference to this variable, where it is referenced, is a strict text substitution procedure, where the string of the value of this variable appears exactly as it was referenced. If there are references to other variables in this variable definition, the referenced variables are expanded at the same time that they are expanded. That is, when the variable is defined, the reference to the other variable in the value of the variable is not replaced, but the variable is replaced with the expansion at the point where it is referenced, and the other variables it references are expanded together. For example, execute the following code:

1 foo =2 a=34  5

Execute "make" will print out "C?", the whole variable substitution process when this: First "$ (foo)" is replaced with "$ (a)", then "$ (a)" is replaced by "$ (b)", and The Last "$ (b)" was replaced with "Hug?". The entire replacement process is done when "echo $ (foo)" is executed. The advantage is that when defined, this type variable can refer to other variables that were not previously defined (which may be defined in subsequent sections, or variables passed through the Make command-line option). Using a variable definition of this style may cause make to fail in the process of infinite variable expansion due to the recursive definition of the variable.

2, the direct expansion type variable

In order to avoid the problems and inconvenience of the "recursive expansion" variable. GNU make supports a variable of another style, called the "direct expansion" type. This style of variable is defined using ": =". When you use ": =" to define a variable, references to other quantities or functions in the value of the variable are expanded when the variable is defined (replacing the variable). So when a variable is defined, it is a string of text that is actually needed, which no longer contains references to any variables.

Note that the "? =" operator, GNU make, also has an assignment operator called conditional assignment "? =". This is called a conditional assignment because the variable is assigned only if it has not previously been assigned a value.

FOO? = Bar　

It is equivalent to:
Ifeq ($ (Origin FOO), undefined)
FOO = Bar
endif

The implication is that if the variable "FOO" is not previously defined, it is assigned a value of "bar". Otherwise, it does not change its value.

Define functions in Makefile:

The GNU make function provides a way to handle file names, variables, text, and commands. Using functions our Makefile can be written in more flexible and robust. A function can be called where it is needed to process the specified text (the text that needs to be processed as a function parameter), and the function is replaced with its processing result where it is called. The expansion of a function call (reference) and a variable reference are expanded in the same way.
The syntax for the GUN make function call:

The GNU make function has a call format similar to a reference to a variable, starting with "$" to represent a reference. The syntax format is as follows:
$ (FUNCTION ARGUMENTS) or ${function ARGUMENTS}

1, calling the syntax format "function" is the name of the functions that need to be called, it should be the name of the function built in. For the user's own function, it needs to be called indirectly through make's "call" function.

2, "ARGUMENTS" is the function of the parameters, the parameter and function name between the use of a number of spaces or [tab] character segmentation (it is recommended to use a space, which not only makes it more intuitive in writing, more importantly, when you are not sure if you can use [tab], avoid unnecessary trouble) If more than one argument is present, the parameters are separated by commas ",".
3. Start with "$", using paired parentheses or curly braces to enclose the function name and parameters (in makefile, parentheses and braces must appear in pairs everywhere). When there is a reference to a variable or function in a parameter, the delimiter (parentheses or curly brackets) used for them is the same as the reference function and does not use two different parentheses. It is recommended to use parentheses uniformly in variable references and function references, so that when you write Makefile using the VIM editor, you use the inline function name, which can be used to make the brightness explicit by using a circle, to avoid spelling errors in the function name. In Makefile you should write "$ (sort $ (x))" Instead of "$ (sort ${x})" and several others.

4, when the function processing parameters, if there is a reference to other variables or functions, the first to expand these references to get the actual contents of the parameters. Before they are processed. The order in which the parameters are expanded is based on the order of the parameters.

5, when writing, the parameters of the function cannot appear the comma "," and the space. This is because the comma is used as a delimiter for multiple parameters, and leading spaces are ignored. In the actual writing of Makefile, when there are commas or spaces as parameters of the function, they need to be assigned to a variable, in the parameters of the function to refer to the variable to implement.

There are some of the inline text (string) processing functions we use in GUN make:

1, $ (subst from,to,text)

Function Name: string substitution function-subst.
function function: Replace the "from" character in the string "TEXT" with "to".
Return value: The new string after replacement.

2, $ (patsubst pattern,replacement,text)

Function Name: pattern substitution function-patsubst.
function function: Search for words separated by spaces in "text" and replace "PATTERN" with "replacement" in "text". The pattern wildcard "%" can be used in the parameter "pattern" to represent several characters in a single word. If the parameter "replacement" contains a "%", then "%" in "replacement" will be the string represented by the "%" in "Tattern". In "Tattern" and "replacement", only the first "%" is treated as a pattern character, and then the pattern character (as a character) is no longer present. If you want the first occurrence of "%" as the character itself and not as a pattern character, you can use the backslash "\" for escape processing (the mechanism of escaping processing and the escape using static mode is consistent).

Return value: The new string after replacement.
Function Description: Multiple spaces between the argument "TEXT" word are merged into a single space when processed, and the leading and trailing spaces are ignored.
3. Sorting function　　　

Function Name: sort function-sort.
function function: The words in the string "list" are sorted by the first letter (ascending), and the duplicated words are removed.
Return value: space-delimited string with no duplicate words.
Function Description: Two functions, sorting and repeating words in a string. One of these features can be used alone.
Example:
$ (Sort foo bar lose foo)
The return value is: "Bar foo lose".

。。。。。。 More function Reference GUN make Chinese manual

In general, when compiling Linux drivers, we need to compile in a cross-compilation environment, so build a cross-compilation environment in a compiled environment. Writing the driver's makefile makes it necessary to develop the path of the kernel that drives dependencies, makefile the following:

1 kern_dir =/xxx/xxx/linux-2.6. 22.6 2 3 All : 4     Make-c $ (kern_dir) m=   5  6clean:  7     make-c $ (kern_dir) m=' PWD ' Modules clean 8     RM-RF Modules.order  9 obj-m    + = Buttons.o

kern_dir=/xxx/xxx/linux-2.6.22.6, this sentence is to assign values to the Kern_dir, determine the kernel source code when using kernel source path.

Make-c $ (kern_dir) m= ' pwd ' modules, this is the rule of makefile: the function of the-C option is to transfer the current working directory to the location you specify, when make is the target of all,-C $ (Kdir) Specify to jump to the kernel source directory to read the makefile there.

m=$ (PWD) indicates then returns from the kernel makefile to the current directory to continue reading, executing the current makefile. M is the variable used in makefile in the kernel root directory, and the "m=" option is to add "M=dir" to the Make modules command when the user needs to compile an external module based on a kernel, and the program will automatically find the module source code in the dir directory you specify. Compile it to generate a KO file. The phrase m= ' pwd ' is used to develop the path of the driver we compiled. This sentence can be written pwd:=$ (shell pwd) m= ' pwd '.

Makefile of the Linux drive series