Makefile rules ③ rule syntax, dependency, wildcard, Directory Search, and target

Rule syntax

The syntax format of the rule is as follows:

Targets: prerequisites

Command

...

Or:

Targets: prerequisites; command

Command

...

In the rule, "targets" can be multiple file names separated by spaces, or a tag (for example, "clean" is executed "). The "targets" file name can use wildcards. The format "A (m)" indicates the file (static library in Linux. file a) member "M" (for information on static library reconstruction, refer to Chapter 11th using make to update static library files ). Generally, a rule has only one target file (we recommend that you do this), and multiple targets are occasionally required in a rule.

Writing rules are a few points of attention:

1. The command part of the rule can be written in two ways: a. The command can be placed in the same line as the target: dependency description. The command is separated from the dependent file list by a semicolon (;) after the dependency file list. B. The command is in the next line of the target: dependency description, which serves as an independent command line. This line must start with a [Tab] character when it is used as an independent command line. In makefile, all rows that start with the [Tab] character after the first rule are processed as commands.

2. the symbol "$" in makefile has a special meaning (indicating the reference of a variable or function). You need to use the symbol "$" in the rule, you need to write two consecutive records ("$ ").

3. As mentioned above, for a long row in makefile, we can use the Backslash "\" to write it to several independent physical rows. Although make has no limit on the maximum length of the makefile text line, we recommend that you do so. It is not only easy to write but also more conducive to reading by others (this is also a reflection of programmer cultivation ).

Dependent Type

There are two different types of dependencies in the GNU make rule:

1. The rules mentioned in the previous chapter use regular dependencies, which is the most common method for writing makefile rules.

2. The other method is not frequently used when we write makefile. It is special and called the "Order-only" dependency.

The regular dependency of a rule (usually multiple dependent files) indicates two things:

First, it determines the order in which the target rule is to be executed (or execute command). It indicates that the target rule is updated (the command line for executing the rule) in what order do you need to execute those rules (commands) to recreate these dependent files (rebuilding all dependent files, using explicit or implicit rules. That is to say, for such a rule: A: B c, the reconstruction of the dependent files B and C must be completed before the reconstruction of target. The process of rebuilding B and C is to execute the rules with file B and C as the target in makefile ).

Secondly, it determines a dependency relationship. If any of the dependent files in the rule is newer than the target file, it is deemed that the target of the rule has expired and the target file needs to be rebuilt.

Sometimes, you need to define such a rule. When updating a target (the target file already exists), you only need to determine whether the target needs to be rebuilt based on the part of the dependency file, instead of recreating the target after any of the dependent files is modified. To achieve this goal, rules need to be classified accordingly. One is to update the rules after these dependency files are updated; the other is to update these dependencies, and you do not need to update the target of the rule. The second class is called the "Order-only" dependency. When writing rules, "Order-only" depends on the pipeline symbol "|", which is used as a dependent file of the target. In the rule dependency list, the regular dependency is on the left side of the MPs queue symbol "|", and the order-only dependency is on the right side of the MPs queue symbol. The rule format is as follows:

Targets: Normal-prerequisites | order-only-prerequisites

Use wildcards for file names

Wildcard characters can be used to indicate a file name in maekfile. The following Wildcards are available: "*" and "?". And "[…]". The usage and meaning of wildcards in makefile are exactly the same as those in Linux (UNIX) Bourne shell. For example, "*. c" indicates all files ending with ". c" in the current working directory. However, in makefile, these wildcard characters cannot be used anywhere. In makefile, the wildcard can appear in the following two scenarios:

1. It can be used in the target and dependency of the rule. Make will automatically match the makefile when reading it (wildcard expansion );

2. In the rule command, wildcard configuration processing is completed when shell executes this command. Wildcards cannot be used directly in other contexts except for these two cases. Instead, the function "wildcard" must be used.

If a rule file name contains a wildcard character ("*", ". when using such a file, escape the wildcard characters in the file name using the backslash. For example, "foo \ * bar" indicates the file "foo * bar" in makefile ". The transfer of some special characters in makefile is basically the same as that in B-SHELL and C language.

The wildcards used in the variable definition will not be configured (therefore, wildcards cannot be used in the variable definition; otherwise, unexpected results may occur in some cases, ). In makefile, a variable is defined as "objects = *. O ". It indicates that the value of the variable "objects" is the string "*. O" (not the list of. O files separated by spaces ). When the variable "objects" is required to represent all. o file columns, you need to use the function "wildcard" (Objects = $ (wildcar *. O )).

Directory Search

General Search (variable vpath)

GNU make can identify a special variable "vpath ". You can use the variable "vpath" to specify the search path of the dependent file. When the dependent file of the rule does not exist in the current directory, make searches for these dependent files in the directory specified by the variable. This variable is usually used to specify the search path of the Rule dependent file. In fact, the "vpath" variable specifies the search path for all files in the makefile, including the rule dependent files and target files.

When defining the variable "vpath", multiple directories to be searched are separated by spaces or colons. Make searches for directories in the order defined by the variable "vpath" (the current directory is always the first one ).

Selective search (keyword vpath)

Another way to set the file search path is to use the make keyword "vpath" (all lowercase ). It is not a variable, but a keyword of make. Its implementation function is similar to the "vpath" variable mentioned in the previous section, but it is more flexible. It can specify different search directories for different types of files (separated by file names. It can be used in three ways:

1. vpath pattern directories specifies the search directory "directories" for all files that conform to the pattern "pattern ". Separate multiple directories with spaces or colons. Similar to the "vpath" variable in the previous section.

2. vpath pattern: Clear the search path set for the file that meets the pattern.

3. vpath: Clear all configured file search paths.

In the vapth usage method, "pattern" must contain the pattern character "% ". "%" Indicates matching one or more characters. For example, "%. H" indicates all files ending with ". H. If "pattern" does not contain the pattern character "%", it is a clear file name, which is the directory where the file is located, we seldom use this method to specify a search path for a single file. In the pattern specified by "vpath", we can use a backslash to reference the character "%" (the same as the reference of other Special Envoy characters ).

Makefile pseudo-Target

A pseudo-target is a target that does not represent a real file name. When executing make, you can specify this target to execute the rule-defined command, sometimes a pseudo target can be called a tag. There are two reasons for using a pseudo-target:

1. avoid the Target defined in our makefile to only execute commands (this goal is to execute some column commands without creating this goal) conflicts with the actual file name in the working directory.

2. Improve the efficiency of executing make, especially for a large project, you may be equally concerned about the compilation efficiency.

If we need to write such a rule: the command defined by the rule is not to create the target file, but to explicitly specify it through the make command line to execute some specific commands. Like common clean goals:

Clean:

RM *. O temp

In the rule, "RM" is not a command to create the file "clean", but to delete all. O files and temp files in the current directory. If the file "clean" does not exist in the working directory, input "make clean". "RM *. otemp" will always be executed. However, if the file "clean" exists in the current working directory, the situation will be different. Similarly, we enter "make clean" because this rule does not have any dependent files, therefore, the target is regarded as the latest command without executing the rule. Therefore, the command "RM" will not be executed. This is not our original intention. To solve this problem, we need to declare the target "clean" as a pseudo target. The method to declare a target as a pseudo-target is to use it as the dependency of the special target. Phony. As follows:

. Phony: clean

In this way, the target "clean" is declared as a pseudo-target, regardless of whether the file "clean" exists in the current directory. Enter "make clean. All "RM" commands are executed. Besides, when a target is declared as a pseudo-target, make will not try to find the implicit rule to create it when executing this rule. This also improves the execution efficiency of make, and does not have to worry about the failure of our expectation due to the duplicate of the target and file name.

Another application of pseudo-targets is in the parallel and Recursive Execution of make.

Force target (no command or dependency Rules)

If a rule does not have commands or dependencies, and its target is not an existing file name. When executing this rule, the target will always be regarded as the latest. That is to say, once the rule is executed, make considers that its target has been updated. When such a target is dependent on a rule, because the dependency is always considered updated, the commands defined in the rule where the dependency is located will always be executed. Let's look at an example:

Clean: Force

Rm $ (objects)

Force:

In this example, the target "force" meets the preceding conditions. As the dependency of the target "clean", it is always considered updated when executing make. Therefore, the command defined by "clean" is always executed when the rule is executed. Such a goal is usually named "force ".

Empty target file

The empty target file is a variant of the pseudo-target. The rule of the target is executed for the same purpose as the pseudo-target file-use the make command line to specify it as the ultimate goal to execute the command defined by the rule. Different from a pseudo-object: This object can be an existing file, but we do not care about the specific content of the file. Generally, this file is an empty file.

The empty target file is only used to record the last time this rule command was executed. In such a rule, the command part will use "Touch" to update the timestamp of the target file after all the commands are completed, and record the last execution time of the Rule command. Make uses the command line to set this target as the ultimate goal. If this file does not exist in the current directory, "Touch" will create an empty file (named as an empty target file name) during the first execution ).

Multi-objective

A rule can have multiple targets. The commands defined by the rule are valid for all targets. A rule with multiple targets is equivalent to multiple rules. The rule command has different effects on different targets, because the automatic ring variable "[email protected]" may be used in the Rule command. Multi-objective rules mean that all targets have the same dependent files.

Although different commands can be used for different targets in multi-target rules (use the automated variable "[email protected]" in the command line). However, the multi-target rules cannot automatically change the dependency file according to the target file (like the command for changing the rule using the automation variable [email protected] in the preceding example ). To achieve this, you need to use the static mode of make.

 

 

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Makefile rules ③ rule syntax, dependency, wildcard, Directory Search, and target