Makefile Usage Summary

1. Makefile Introduction

Makefile is used in conjunction with the Make command.

Many large-scale projects are compiled through Makefile, and if there is no Makefile, the dependencies between the various libraries and code in many projects do not know how complex.

Makefile's ability to organize processes is so strong that it can be used not only to compile projects, but also to organize our usual daily operations. This requires everyone to play their own imagination.

This blog is based on {essence} with me to write Makefile and collation, some limitations, added some examples.

Thank you very much for GUNGUYMADMAN_CU for providing such an exhaustive introduction to Makefile, which is the makefile Chinese document I have been looking for.

1.1 Makefile main 5 parts (show rules, cryptic rules, variable definitions, document instructions, notes)

The makefile basic format is as follows:

Target ...: Prerequisites    ... Command    ...    ...

which

• Target-the object file, which can be either an object or an executable file
• Prerequisites-The file or target required to generate the target
• Command-make the command to execute (any shell command), the command in makefile must start with [tab]

1. Show rules:: Shows how to generate one or more target files (including generated files, file dependent files, generated commands)
2. Cryptic rules:: The rules that are enforced by the auto-derivation function of make
3. Variable definition:: variable defined in makefile
4. File indication:: Makefile references other makefile; Specify the valid part of the makefile; Define a multi-line command
5. Note:: Makefile only line comment "#", if you want to use or output "#" character, you need to escape, "\#"

1.2 How GNU make works

1. Read Master makefile (other makefile can be referenced in the main makefile)
2. Read into other makefile of include
3. Initialize the variables in the file
4. Derivation of cryptic rules and analysis of all rules
5. Create a dependency chain for all target files
6. Depending on the dependencies, decide which targets to regenerate
7. Execute Build command

2. Makefile Primary Grammar 2.1 Makefile Rules 2.1.1 Rule Syntax

There are 2 of rules: dependencies and methods for generating targets.

There are 2 types of syntax:

Target ...: Prerequisites    ... Command    ...

Or

Target ...: prerequisites; Command    command    ...

* Note * command is too long, you can use "\" as Line break

wildcard characters in a 2.1.2 rule

• *:: Denotes any one or more characters
• ? :: Denotes any one character
• [...] : Ex. [ABCD] denotes any character in a,b,c,d, [^ABCD] represents a character other than A,b,c,d, [0-9] represents any number in 0~9
• ~:: Indicates the user's home directory

2.1.3 Path Search

When a large number of source files are involved in a makefile (these source files and makefile are most likely not in the same directory),

At this point, it is better to clear the path of the source file in makefile, convenient for compile-time lookup. There is a special variable in the makefile VPATH is the completion of this function.

After VPATH is specified, if the file or dependent file is not found in the current directory, Makefile back to the path specified in VPATH to find it:

VPATH How to use:

• Vpath <directories>:: When a file is not found in the current directory, search from <directories>
• Vpath <pattern> <directories>:: Files that conform to <pattern> format search from <directories>
• Vpath <pattern>:: Clear File search path in <pattern> format
• Vpath:: Clear all the file paths that have been set

# example 1-When a file is not found in the current directory, sequentially from the SRC directory: Find files in/parent-dir directory Vpath src:.. /parent-dir   # The files ending in Example 2-. h are looking for Vpath%.h from the./header directory./header# Example 3-clears the rule set in Example 2 Vpath%.h# Example 4-Clears all Vpath settings Vpath

2.2 Variables in the Makefile 2.2.1 Variable definition (= or: =)

OBJS = PROGRAMA.O Programb.oobjs-add = $ (OBJS) programc.o# or Objs: = PROGRAMA.O Programb.oobjs-add: = $ (OBJS) PROGRAMC.O

where = and: = The difference is that: = Only use the previously defined variables, = can use the variables defined later

Test =

# makefile Content OBJS2 = $ (OBJS1) programc.oobjs1 = PROGRAMA.O Programb.oall:    @echo $ (OBJS2) # Bash to execute make, you can see that although OBJS1 is in OBJS2 is defined later, but can be used in advance in OBJS2 $ MAKEPROGRAMA.O programb.o PROGRAMC.O

Test: =

# makefile Content OBJS2: = $ (OBJS1) Programc.oobjs1: = PROGRAMA.O programb.oall:    @echo $ (OBJS2) # Bash to execute make, you can see the OBJS2 in the $ (OBJS1) is empty $ makeprogramc.o

2.2.2 Variable substitution

# makefile Content SRCs: = programa.c programb.c PROGRAMC.COBJS: = $ (SRCS:%.C=%.O) All:    @echo "SRCS:" $ (SRCS)    @echo "OBJ S: "$ (OBJS) # bash run make$ makesrcs:  programa.c programb.c programc.cobjs:  programa.o programb.o PROGRAMC.O

2.2.3 Variable Append value + =

# makefile Content SRCs: = programa.c programb.c Programc.csrcs + = Programd.call:    @echo "SRCS:" $ (SRCS) # run make$ makes in bash RCS:  programa.c programb.c programc.c programd.c

2.2.4 variable override override

The function is to enable variables defined in the makefile to override the variables specified in the Make command argument

Grammar:

• Override <variable> = <value>
• Override <variable>: = <value>
• Override <variable> + = <value>

Here's an example of how override works:

# Makefile Content (No Override) SRCs: = programa.c programb.c programc.call:    @echo "SRCS:" $ (SRCS) # bash run make$ make srcs= Nothingsrcs:  nothing################################################## Makefile content (with override) override SRCs: = PROGRAMA.C programb.c programc.call:    @echo "SRCS:" $ (SRCS) # bash run make$ make Srcs=nothingsrcs:  programa.c PROGRAMB.C PROGRAMC.C

2.2.5 Target Variable

The effect is to limit the scope of the variable to this target, rather than the variable defined in the previous example, which is valid for the entire makefile.

Grammar:

• <target ...>:: <variable-assignment>
• <target ...>:: Override <variable-assignment> (override action see Introduction to Variable Overrides)

Example:

# Makefile content SRCs: = programa.c programb.c Programc.ctarget1:target1-srcs: = Programd.ctarget1:    @echo "SRCS:" $ (SRCS    @echo "SRCS:" $ (TARGET1-SRCS) Target2:    @echo "SRCS:" $ (SRCS)    @echo "SRCS:" $ (TARGET1-SRCS) # Bash execution make$ Make Target1srcs:  programa.c programb.c programc.csrcs:  programd.c$ make Target2     <--Target2 not displayed in $ ( TARGET1-SRCS) SRCs:  programa.c programb.c Programc.csrcs:

2.3 Makefile Command prefix

When writing a shell command in Makefile, you can add 2 prefixes @ and-or without a prefix.

The 3-format shell commands differ in the following ways:

• No prefix:: output command executed and result of command execution, stop execution if error occurs
• Prefix @:: Output only the result of command execution, stop execution if an error occurs
• Prefix-:: Command execution is wrong, ignore error, continue execution

Example:

# Makefile content (without prefix) all:echo "no prefix" Cat this_file_not_exist echo "error after command" <--This command will not be executed # Bash execution make$ Makeecho "No prefix" <--the command itself is displayed without a prefix <--command execution results are shown in Cat This_file_not_existcat:this_file _not_exist:no such file or directorymake: * * * [all] Error 1########################################################### # Makefile content (prefix @) All: @echo "no prefix" @cat this_file_not_exist @echo "command after error" <--This command will not be executed # Bash execution ma  ke$ make does not have a prefix <--only the result of the command execution, does not show the command itself cat:this_file_not_exist:No such file or directorymake: * * [All] Error 1############################################################ Makefile content (prefix-) All:-echo "no prefix"-cat this_fi                    Le_not_exist-echo "command after error" <--This command will be executed # Bash execution make$ makeecho "no prefix" <--the command itself shows no prefix  <--command Execution results show cat this_file_not_existcat:this_file_not_exist:No such file or directorymake: [All] Error 1 (ignored) echo "errorAfter the command "<--error after the command will also show the error after the command <--error after the command will also be executed 

2.4 Pseudo-target

A pseudo-target is not a "target" and does not generate a target file like a real target.

A typical pseudo-target is the clean pseudo-target used in Makefile to clear intermediate files during compilation, in the following general format:

. Phony:clean   <--This sentence is not OK, but it is best to add clean:    -rm-f *.O

2.5 references to other Makefile

Syntax: include <filename> (filename can contain wildcard characters and paths)

Example:

# Makefile Content All:    @echo "master Makefile Begin"    @make other-all    @echo "main Makefile end" include./other/makefile#./ Other/makefile content Other-all:    @echo "Other Makefile begin"    @echo "Other Makefile End" # Bash execute make$ lltotal 20k-rw -r--r--1 wangyubin wangyubin  Sep 16:13 makefile-rw-r--r--1 wangyubin wangyubin  11K Sep 16:15 Makefile. ORG   <--This file without tube Drwxr-xr-x 2 wangyubin wangyubin 4.0K Sep 16:11 other$ ll other/total 4.0k-rw-r--r--1 wangyubin Wangyubin Sep 16:11 makefile$ make

Makefile Usage Summary