Memory management Notes (paging, segmentation, logical address, Physical address) "Go"

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1. Physical Address and logical address

Physical Address : The address that is loaded into the memory address register, the true address of the memory unit. The memory addresses that are transmitted on the front-end bus are physical memory addresses, starting from 0 to the highest available physical memory. These numbers are mapped to the actual memory strip by North Bridge (Nortbridge chip). Physical addresses are explicit, end-use numbers on the bus, do not have to be converted, do not have to be paged, and do not have privilege-level checks (no translation, no paging, no privilege checks).

Logical Address : The address generated by the CPU. Logical addresses are internally and programmatically used and are not unique. For example, you can read the pointer variable itself (& operation) in the C-language pointer programming, which is actually the logical address, which is relative to the address (offset address) of your current process data segment, not to the absolute physical address.

Why do you have these two types of addresses?

The reason for personal sleep is that the logical address assignment is more flexible, can be allowed not unique, it seems more intuitive, for example, a section of code allocation of arrays, logical addresses are contiguous, but on the physical address, the array occupied by the page may be scattered, the physical address is discontinuous, so that the program can be understandable impact. In addition, with the concept of logical address, virtual memory technology can be used.

2. Paging, paging memory management scheme

(1) The maximum effect of paging is that the physical address space of the process can be non-contiguous.

The physical memory is divided into a small block of pieces, each of which is called a frame. When allocating memory, the frame is the smallest unit at the time of allocation, and at least one frame is given. In logical memory, the concept that corresponds to a frame is the page.

The logical address is represented by the page offset, which is the first part of the page number.

For example, a known logical space address is 2^m bytes (that is, the length of the logical address is M-bit), and the page size is known as 2^n bytes. Then altogether there can be 2^ (m-n) pages. Therefore, the page number portion will occupy the M-n bit, followed by the n bit, used to store the page offset.

For example, the page size is 4B, and the logical memory is 32B (8 pages), the page number of the logical address 0 is 0, the page number 0 corresponds to frame 5, so the logical address is mapped to the physical address 5*4+0=20. Logical Address 3 maps the physical address 5*4+3=23. The logical address 13 (4*3+1, the page number is 3, the offset is 1, so the frame number is 2), mapped to physical address 9.

The use of paging technology does not produce external fragments (memory is divided into frames), but may produce internal fragments (the frame is already the smallest unit, so there may be no space inside the frame).

On average, each process can have an internal fragment of half the frame size, calculated by probability.

(2) Hardware implementation of the page table

The page table in the previous section is the key to translating the logical address into a physical address. So how does the page table be stored?

Each operating system has its own method to save the page table. Most will assign a page table to each process. Now because the page table is larger, so put in memory (formerly placed in a set of special registers), its pointer exists in the Process Control block (PCB), when the process is selected to run by the scheduler, the system takes its page table pointer out of the process control block and into the user register. You can then access the page table based on this first address.

The page table is stored in TBL (translation look-aside buffer, translation fallback buffer)+ memory. The TBL is actually a set of fast memory associated with a hardware buffer. Without TBL, the operating system requires two memory accesses to complete the conversion of the logical address to the physical address, the access page is counted once, and the lookup is counted once in the page table. A small subset of entries in a page table are stored in TBL, and entries are stored as key-value pairs.

(3) Data Structure of page table

A.

This year is 2013, the existing notebook computer, memory address space is generally more than 2^32 bytes. For a computer system with 32-bit logical address space, if the system has a page size of 4KB (2^12b), then the page table can have 2^ (32-12), which is the distances entry, assuming that each entry occupies 4B, each process requires a 4MB physical address space to hold the page table itself. Furthermore, the page table itself needs to be allocated in contiguous memory.

To do this,hierarchical Paging (hierarchical paging) is presented, in effect, the page number is divided into two parts, the first part as the index, the second part as the page number offset.

Take an example of a 4KB page size 32-bit system. A logical address is divided into 20-bit page numbers and 12-bit page offsets. Because the page table is paged, the page number can be divided into 10-bit page numbers and 10-bit page offsets. Such a logical address represents the following form:

The address translation process is as follows:

The address is converted inward, so this method is also known as the forward-mapped page table (Forward mapping table).

B. Hashed page Tables Hash page table

A common way to handle more than 32-bit address space is to use the Hashed page table (hash page tables)with a virtual page number as the hash value. Each entry in the hash page table includes an element of a linked list that texts hash the same location. Each element has three fields: a virtual page number, a mapped frame number, and a pointer to the next element in the linked list.

Personally, the address translation of the hash page table is actually a Chaining (link) way, that is, a hash function overflow processing method (another overflow processing mode is called open addressing, open addressing), the process is as follows:

The logical address needs to be represented by an address space greater than 32bit, but the operating system still has only 32bit to represent the address. At this point, people think of the virtual page address, the virtual address can be within the range of 32bit representation, and then use the hash function to complete the logical address to the virtual address mapping, due to fewer virtual addresses, the hash function overflow, here use chaining to resolve overflow.

The page number in the logical address (p in) is computed by the hash function, which calculates the page number in the virtual address, which can be addressed in the hash table as O (1), using p compared to the first field of each element in the list. If matched, the corresponding frame number is used to form the physical address. If it does not match, the next node in the list is compared to find a matching page number.

C. Inverted page Table Reverse page

Time relationship, this paragraph temporarily skipped.

3. Segmentation, segmented memory management scheme

There is an unavoidable problem with paging memory management: the separation of memory and actual memory from the user's perspective. Imagine a main function code that contains a call to the SQRT function. According to the writer's understanding, when this code runs, the operating system should allocate memory to: symbol table (used at compile time), stack (store local variable and function parameter value), SQRT code snippet, main function code snippet, etc. In this way, the writer can conveniently point out: "The function sqrt the fifth instruction of the memory module" to locate an element. In fact, because of the management of paging, everything is scattered in the physical memory of each frame, not the writer's understanding to divide the module.

Segmentation's memory management approach can support this approach. The logical address space consists of a set of segments. Each segment has a name and a length. The address specifies the segment name and the intra-paragraph offset. So the user specifies the address by two quantities: segment name and offset. Segments are numbered and are referenced by segment numbers rather than by segment names. The logical address is therefore composed of ordered pairs:

<segment-number,offset> (< section number S, offset d> in segment)

Segment Offset d because it is between the 0 and the segment bounds, if it is legal, then add to the base address to get the required bytes in physical memory addresses. Therefore, the segment table is a set of base address and bounds register pairs.

For example, there are 5 segments, numbering 0~4, for example segment 2 is 400B starting at position 4300, and a reference to segment 2 of 53 bytes is mapped to position 4300+53=4353. The reference to segment 0 byte 1222 triggers an address error because the segment is only 1000B long (bounds 1000).

4. Consolidation of segmentation and paging management scenarios

On an existing Intel-compatible computer (x86), the memory management scenario used is a management scenario for segmented and paginated merging.

In this scenario, the logical address, as described in the previous section, is the offset of the relative address in the specified segment by a segment identifier, expressed as the [segment identifier: offset within paragraph].

What is the process of such a logical address translation? As shown in the following:

The conversion process begins when the CPU executes an instruction that references a memory address. The first step is to convert the logical address into a linear address . But why not skip this step and let the software directly use a linear address (or physical address?). The reason is mainly because:

(1) Intel's update is progressive rather than revolutionary, and the new processor needs to be compatible and retain past settings. For specific reasons, the blog Memory Translation and segmentation (http://blog.csdn.net/drshenlei/article/details/4261909) is more clearly spoken.

(2) As mentioned in the previous section, using segment memory management, you can easily address protection (the same type of address logical address together).

The following is the part of the logical address to the linear address.

In the IBM OS/2 32-bit version of the operating system, and the Intel 386 environment. The memory allocation method used by the operating system is the way in which fragmentation and paging are merged.

The logical address is actually a pair of < selectors, offset >.

The contents of the selector are as follows:

From the left, the 13-bit is the index (or the segment number), through which you can navigate to the Segment Descriptor (segment descriptor), while the segment descriptor can actually record the location and size information about a segment, as well as the state information of the access control. Segment descriptors are typically made up of 8 bytes. Because the 8B is large, and Intel is going backwards compatible, the segment register is still defined as 16-bit (although each segment register actually has a 64-bit-long invisible part, but for programmers, the segment register is 16-bit), it is clear that We cannot directly refer to the 64-bit segment descriptor by 16-bit the length of the segment register. So in a logical address, only 13bit records its index. The true segment descriptor is placed in the array.

This in-memory array is called the GDT ( Global descriptor Table), and Intel's designer door provides a register GDTR to store the GDT's entry address. After the programmer sets the GDT to a location in memory, the LGDT instruction will load the GDT's entry address into this register, from which the CPU accesses the GDT based on the contents of this register as the GDT's entry.

In addition to the GDT, there is the Ldt ( Local Descriptor table, native description table), but unlike GDT, the LDT can exist in the system more than one, each process can have its own LDT. The memory address of the LDT is in the LDTR register.

The TI bit in the previous figure is used to indicate whether the segment descriptor pointed to by this index is in the Global description table or in the local description table. =0, indicating the use of gdt,=1 in the LDT.

RPL bit, accounting for 2bit, is to protect the information bit, have not carefully understand this piece, temporarily not write.

When found, the segment descriptor is followed by an offset, which is the linear address. The conversion process is as follows:

In an Intel 386 environment, a linear address is converted to a physical address, and in the second section of paged memory management, the logical address is converted to a physical address in a hierarchical paging similar way. Such as.

The whole process of address translation for Intel 80386 is as follows:

The memory management part is one of the core functions of the operating system, this time will be part of the theory, one is to review, the second is to sketchy for in-depth learning operating system to prepare.

Memory management Notes (paging, segmentation, logical address, Physical address) "Go"