| 16 color palette registers and 256 color registers |
4. Change the screen color
There are two steps: 1. Select the color palette register based on the color number
Ii. Modify the color palette register
The two steps can be completed through the int 10 h interrupt call of Bion.
Step 1 entry: Ah = 10 h
Al = 07 h
BL = color (0-15)
Exit: bH = palette Register number (0-255)
Step 2 entry: Ah = 10 h
Ah = 10 h
BX = palette Register number
DH = red weight in color (0-63)
Ch = green component in color (0-63)
CL = blue weight in color (0-63)
Exit: None
Note 1: changing colors indicates changing the brightness of various colors.
NOTE 2: When the 12 h mode is initialized, the screen edge and background both use register 0 (black ). Using a ROM-BIOS interrupt call (10 h) enables edge color registers to use another palette register.
Entry: Ah = 10 h
Al = 01 H
BH = palette Register number (0-255)
Exit: None
You can point BH to an uncommon color palette register (for example, 0ffh) and modify the color composition of 0ffh to display 17 colors on the same screen. That is, the edge color register does not use one of the 16 color palette registers.
5. Change the default 16 color settings
The ROM-BIOS (INT 10 h)
Entry: Ah = 10 h
Al = 00 h
BL = color (0-15)
BH = palette Register number (0-255)
Exit: None
Note: changing the color indicates that a color number uses the specified color instead of the default color. changing the color of a color number (0) can change the background color.
6. Take the colors of the current screen
BiOS display interrupt (10 h) Call
Entry: Ah = 10 h
Al = 15 h
BX = palette Register number (0-255)
Outlet: DH = red weight in color (0-63)
Ch = green component in color (0-63)
CL = blue weight in color (0-63)
Note: If you do not know the color palette register corresponding to a color number, you can use the 10h function to call the 07 Sub-function.
* Enable and disable screen display
Entry: Ah = 12 h
Al = switch Screen Display (0 = on, 1 = Off)
BL = 36 h
Exit: None
Note: If you do not want people to see the drawing process, you can close the display first, and then open the display after the painting is finished. This also has a pop-up effect.
VII. Common vgacard registers
1. Time Series Generator
Control the total timing signals of all VGA functions and complete some storage address decoding. there are five registers, and two I/O addresses (3c4h and 3c5h) are reused. 3c4h is the index register address. used to select the current Register.
(1) The timing line of the time series generator is configured in the clock mode register (index No. 01 H), which does not need to be modified in general applications. the 4th-bit Register determines whether the pixel/VGA is encoded in bytes or words. This parameter is used for smooth screen scrolling.
(2) The color plane allows the write register (02 h) to control whether the processor is allowed to write the color plane. by selectively allowing certain color planes to be written, a specific image can be displayed on the screen. The default value is 0fh (all planes can be written)
Bit definition: 7-4 Reserved
3rd-bit write plane 3 (= 1, allowed)
2nd-bit write plane 2 (= 1, allowed)
1st-bit write plane 1 (= 1, allowed)
0th-bit write plane 0 (= 1, allowed)
(3) reset register (00 h)
(4) character generator Selection Register (03 h)
(5) storage mode register (04 H)
2. graphic controller
Perform logical operations (and, Or, exclusive or, etc.) on the data to be written into VRAM, including nine internal registers, reusing two I/O addresses (3ceh and 3cfh ), 3ceh is the index register address. Before performing any drawing operation, you should also set the color plane of the time series generator to allow the write register to select the color plane (of course, you can do nothing with only the default value)
(1) placement/Reset register (index No. 00 h)
This register is used to store the data written to VRAM. This register should be used in conjunction with the allowed slot/Reset register.
Bit definition: 7-4 Reserved
Fill data of 3rd-bit plane 3
Fill data of 2nd-bit plane 3
Fill data of 1st-bit plane 1
Fill data of 0th-bit plane 0
Default Value: all bits are 0.
(2) permitted position/Reset register (index No. 01 H)
Determines which planes receive filled data from the set bit/Reset register. Any prohibited set/Reset plane will be filled in with the processing output data of the general processor (CPU.
Bit definition: (the default value is 0)
7-4 Reserved
3rd bits can be set to 3 bits/RESET (= 1) on the plane)
2nd bits can be set to 2 bits/RESET (= 1) on the plane)
1st BITs allow/RESET (= 1)
0th BITs allow 0 placement/RESET (= 1 allowed) on the plane)
(3) Color comparison register (index No. 02 h)
Used to quickly find the specified pixel in VRAM. color comparison registers can compare all four display plane data with the reference color in a single read storage period. and report whether the color of each pixel position matches. this register is particularly effective in the graphic area Filling Algorithm for Boundary lookup. this register must be used together with the mode register (the default value of all display modes is 0)
Bit definition: 7-4 Reserved
Color comparison value of 3rd-bit plane 3
Color comparison value of 2nd-bit flat 2
Color comparison value of 1st-bit plane 1
0th-bit flat 0 Color comparison value
(4) Data shift and function Selection Register (index No. 03 h)
Two independent functions are controlled: Data Writing shift and logical operations on Data Writing. in the write cycle, data can be shifted to 0-7 digits. you must select the write mode 0 (see the mode register) to allow shift. the function Selection bit provides basic hardware support for VRAM read/write operations.
Bit definition: (0 by default)
7-5 reserved
4-3-bit function Selection bit: = 0 without modifying data
= 1 write data and latches
= 2 write data or latches
= 3 Write Data XOR latches
2nd-0 Data shift digits
NOTE: If both the shift and logical operation are permitted, the logical operation is performed after the shift. each color plane has a corresponding one-byte lock. Therefore, 32-bit data can be loaded into the lock at the same time during a VRAM read period.
(5) read plane Selection Register (index No. 04 H)
Determines the color plane that the processor can read (except for the Color comparison method), that is, the color comparison method is not controlled.
Bit: (0 by default)
7-2 reserved
1-0 defines the readable color plane (0-3)
(6) method register (index No. 05 h)
Most of these bits should not be modified, but two of them are useful, that is, the write mode bit and the color comparison mode allow bit. The Write mode controls how the processor data is written into VRAM.
Note: If the application needs to modify the mode register, the 7-4 bit status must be protected.
Bit definition: 7th bit reserved (0)
6th-bit, 256 colors (for VGA only)
5th-bit shift register method
4th odd/even
The 3rd-bit Color comparison method can work (= 1: Work)
2nd-bit reservation
1-0 bit write mode: = 0 processor direct write
= 1 the content of the latch is used as the write data.
= 2 fill in the nth color plane with the Nth (0-3) bit value of the processor data.
= 3 not used
Note: Write mode 0: usually used, which is also the default state. It allows the processor data to be directly written to VRAM, and allows the placement, reset, shift, shield, and, or, exclusive or other functions (Other Write methods are not allowed)
Write Method 1: it can be used to quickly copy data from one location in VRAM to another location. A write operation on VRAM by the processor reads one byte of data from each of the four color planes and locks the 32-bit data to the lock of the processor, A write operation sent by the processor to VRAM will write 4 bytes of data back to the other address of the display memory (as long as all four color planes allow write) this method can be used to construct Screen Block quick copy or mobile functions.
Write Method 2: when used with bit shielding registers, the compressed pixels are converted into plane pixels and written into the color plane.
(7) hybrid register (index No. 06 h)
After the BIOS mode is selected for initialization, it should not be modified.
(8) color ignore register (index No. 07 h)
Used in combination with the color comparison method. This register shields a specific plane from being tested during the Color comparison period.
Bit definition: 7-4 Reserved
The I-th bit ignores the plane I (I =, 2, 3)
(9) Bit shielding register (index No. 08 h)
Blocks some digits so that they are not modified during the read/write cycle. A value of 0 in the bit shielding Register indicates that during one write process of the monitor, the bit will be from the latch data, not from the output data of the processor. the shielding function is enabled. before writing, you must perform a read operation to load the correct data into the latches.
Note: After completing the tasks for these registers, you should make them the initial default values!
3. CRT controller (not suitable for modification, easy to damage CRT)
The index address is 3d4h and the data port address is 3d5h. |
