Category: ARM Architecture 2011-07-22 00:22 2632 people read comments (10) Collection Report timer import system c Programming Samsung
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Tip: If the reader does not understand the ARM interrupt mechanism, I recommend reading the other three articles first: S3C2440 system interrupt ARM processor exception handling ARM system interrupt generation process
First. Overview
The S3C6410 interrupt controller consists of two VICs (Vectored Interrupt Controller, ARM PrimeCell) and two TZIC ’s (TrustZone Interrupt Controller SP890).
The two TZIC's and VIC's work well together to support 64 interrupt sources. However, from the hardware manual provided by Samsung, we have a thorough understanding of the VIC interrupt working method. We also need to download the VIC controller instruction manual, ARM PrimeCell Vectored Interrupt Controller (PL192) from ARM. Reading this manual can help us understand VIC well. Interrupt control principle.
Second. Features
The characteristics of the vector interrupt controller of S3C6410 are as follows:
l Each VIC controller contains 32 vector interrupts
l Fixed hardware interrupt priority level
l Programmable interrupt priority
l Support hardware interrupt priority masking
l Programmable hardware interrupt priority mask
l Can generate general interrupts and fast interrupts
l Can generate software interrupt
l Native interrupt status
l Interrupt request status
l Support privileged mode to restrict access
As shown in Figure 1-1.
mini6410 interrupt controller-VIC interrupt controller
Figure 1-1 S3C6410 interrupt controller
Third, the interrupt source
The S3C6410 interrupt sources are shown in the following table:
Table 1-1 Interrupt sources
Fourth, VIC register
The base address of VIC0 is 0x71200000, and the base address of VIC1 is 0x71300000
Control register address = offset address + VICn base address
1.Interrupt status register
When the corresponding interrupt is enabled and its interrupt type is selected as a general interrupt, this register indicates the corresponding interrupt status and indicates whether an interrupt is generated.
2. Fast interrupt status register
When the corresponding interrupt is enabled and its fast interrupt type is selected, this register indicates the corresponding interrupt status, and indicates whether a fast interrupt is generated.
3. Pre-interrupt status register
4. Interrupt selection register
Select the corresponding interrupt signal type as general interrupt or fast interrupt.
5. Interrupt enable register
Enable the corresponding interrupt signal. The enable interrupt signal can only pass through this register. If the interrupt is disabled using the VICxINTENCLEAR register, all interrupts are disabled by default after a system reset.
6. Interrupt source disable register
This register is used to clear the interrupt signal enabled by the VICxINTENABLE register.
7. Software interrupt register
8. Software interrupt source clear register
9. Protected mode enable register
Protected mode is disabled by default. Protected mode is turned on by writing 1. All interrupt registers can be accessed only in privileged mode.
10. Software Priority Mask Register
Whether to enable software interrupt priority.
11. Chained Vector Priority Register
12. Vectored Interrupt Handler Address Register
Each register corresponds to the ISR handler address of an interrupt source.
13. Vectored Interrupt Priority Register
14. Vector Address Register
This register stores the address
of the ISR interrupt service routine currently being processed. When an interrupt is currently being processed, its value can only be read from this register, and any value written to this register when the interrupt is processed can clear its value.
External interrupts
GPIO
The S3C6410 contains 187 multi-function input / output pins. It is classified into 17 ports by group. As shown in the table below.
characteristic
l Support 127 external interrupts
l 187 multi-function pins
l Control the state of the pins in sleep mode (except pins GPK, GPL, GPM and GPN)
Since 127 pins can be used to generate external interrupts, the S3C6410 divides them into 10 groups in order to facilitate the management of different external pins as interrupt sources.
The external interrupt is composed of 10 groups of interrupt signals from 0 to 9. Only external interrupt group 0 can wake up when the system is stopped or in sleep mode. In Idle mode, any interrupt signal can wake the system.
Table 1-2 lists the external interrupt control registers. Interrupt signals in external interrupt group 0 have dedicated pins. Compared to other interrupt groups, each interrupt signal in this group can be set in detail. As shown in Table 1-2.
Table 1-2 External interrupt source grouping
2. External interrupt number
Set the corresponding GPIO as an external interrupt pin function and set the external interrupt trigger mode. When an external interrupt is generated, the interrupt signal is not masked by the corresponding mask register (external interrupt group 0 is EINT0MASK, other interrupt groups are EINTxxMASK) , Will enter the external interrupt source suspend register (external interrupt group 0 is EINT0PEND, other interrupt groups are EINTxxPEND), if there are multiple external interrupt signals generated at this time, arbitration of interrupt priority should be performed.
By setting the PRIORITY register to set whether the 10 interrupt groups perform priority rotation, usually we can use the default value.
Figure xxx Priority Arbitration Diagram
The highest priority interrupt signal arbitrated into the VIC controller. As can be seen from the table xxx interrupt sources, only 127 external interrupt signals in the VIC controller share 5 multiplexed signals INT_EINT0 ~ INT_EINT4 corresponding to them. The corresponding relationship is shown in the following table.
Therefore, if the CPU is interrupted by an external interrupt signal corresponding to one of INT_EINT0 ~ INT_EINT4, an interrupt signal is generated. This information is not enough to confirm where the interrupt signal source comes from, but also to determine the external interrupt source pending register.
mini6410 interrupt controller-VIC interrupt controller
Start.S [cpp] view plain copy; led_on Michaeltang 2011-05-11 EXPORT INIT AREA INIT, CODE, READONLY; This directive defines a code segment, the segment name is INIT2440, the attribute is read-only ENTRY Reset; reset exception handling entry ; ####################################; set ROM size; ldr r0, = 0x70000000 orr r0, r0, # 0x13
