MIPI Agreement Chinese detailed

First, MIPI
MIPI (Mobile industry processor interface) is the abbreviation for mobile industry Processor interface. MIPI (Mobile industry Processor interface) is an open standard developed by the MIPI Alliance for mobile application processors.
The specifications that have been completed and are being planned are as follows:

Ii. MIPI DSI Specification for the MIPI Alliance
1. Noun explanation
DCs (Displaycommandset): DCS is a standardized set of commands for display modules in command mode.
DSi, CSI (Displayserialinterface, Cameraserialinterface
The DSi defines a high-speed serial interface between the processor and the display module.
The CSI defines a high-speed serial interface located between the processor and the camera module.
d-phy: Provides a physical layer definition of DSI and CSI
2. DSI Layered Structure
DSI is divided into four layers, corresponding to d-phy, DSI, DCS specification, hierarchical structure diagram as follows:
The PHY defines the transmission medium, the input/output circuit and the clock and signal mechanism.
Lane Management layer: send and collect data streams to each lane.
Low Level protocol layer: Defines how framing and parsing, and error detection.
Application layer: Describes high-level encoding and parsing data streams.

3. Command and video mode
DSI compatible Peripherals Support command or video operation mode, which mode is determined by the architecture of the peripheral
Command mode refers to the use of sending commands and data to a controller with a display cache. The host controls peripherals indirectly through commands. Command mode with bidirectional interface
The video mode refers to the real pixel stream when it is transferred from the host to the peripheral. This mode can only be transmitted at high speed. To reduce complexity and cost savings, a system that only uses video mode may have only one one-way data path

Iii. introduction of D-phy
1. D-phy describes a synchronous, high-speed, low-power, low-cost PHY.
• One PHY configuration consists of
• One Clock Lane
• One or more data lane
• Two lane PHY configurations such as

• Three main lane types
• One-Way Clock lane
• One-way Data lane
• Bidirectional Data Lane
d-phy mode of transmission
• Low power (Low-power) signal mode (for control): 10MHz (max)
• High-speed (high-speed) signal mode (for high-speed data transfer): 80Mbps ~ 1gbps/lane
D-phy Lower level protocol specifies that the minimum data unit is a byte
• The data must be sent low in front, high in the rear.
D-phy for mobile applications
DSI: Display serial interface
• One Clock Lane, one or more data lane
CSI: Video Serial Interface
2. Lane Module
PHY consists of d-phy (Lane module)
d-phy may contain:
• Low power transmitter (LP-TX)
• Low power receiver (LP-RX)
• High-speed transmitter (HS-TX)
• High-speed receiver (HS-RX)
• Low Power Competition Detector (LP-CD)
• Three main lane types
• One-Way Clock lane
Master:hs-tx, Lp-tx
Slave:hs-rx, Lp-rx
• One-way Data lane
Master:hs-tx, Lp-tx
Slave:hs-rx, Lp-rx
• Bidirectional Data Lane
master, Slave:hs-tx, Lp-tx, Hs-rx, Lp-rx, LP-CD
3. Lane Status and Voltage
Lane Status
lp-00, LP-01, LP-10, LP-11 (single-ended)
hs-0, HS-1 (differential)
Lane Voltage (typical)
lp:0-1.2v
hs:100-300mv (200mV)
4. Operation mode
• Three operating modes for data lane
Escape mode, high-speed (Burst) mode, Control mode
• Possible events starting from the stop state of the control mode are:
Escape mode Request (LP-11→LP-10→LP-00→LP-01→LP-00)
High-speed mode request (LP-11→LP-01→LP-00)
turnaround Request (lp-11→lp-10→lp-00→lp-10→lp-00)
Escape mode is a special operation of the data Lane under LP state
• In this mode, you can enter some additional functions: LPDT, Ulps, Trigger
• Data Lane enters escape mode via lp-11→lp-10→lp-00→lp-01→lp-00
• Once you enter escape mode, the sender must send 1 8-bit commands to respond to the requested action
escape mode uses Spaced-one-hot Encoding
• Ultra-low power status (ultra-low power state)
• In this state, the lines is in an empty state (LP-00)
• Ultra-low power state of Clock Lane
• Clock Lane enters Ulps state via lp-11→lp-10→lp-00
• Exit this state via lp-10→twakeup→lp-11 with a minimum twakeup time of 1ms
• High-speed data transfer
• The behavior of sending high-speed serial data is called high-speed data transfer or triggering (burst)
• All lanes doors are synchronized and the end time may be different.
• The clock should be in high-speed mode
• Transmission process under each mode operation
• The process of entering escape mode: Lp-11→lp-10→lp-00→lp-01→lp-00→entry CODE→LPD (10MHz)
• Procedure to exit escape mode: LP-10→LP-11
• The process of entering high-speed mode: Lp-11→lp-01→lp-00→sot (00011101) →hsd (80Mbps ~ 1Gbps)
• The process of exiting the high-speed mode: eot→lp-11
• Control mode-BTA transfer process: lp-11→lp-10→lp-00→lp-10→lp-00
• Control mode-BTA receive process: lp-00→lp-10→lp-11
• state transition diagram

Iv. Introduction of DSi
1, DSI is a lane expandable interface, 1 clocks lane/1-4 Data Lane
DSI compatible Peripherals support 1 or 2 basic operating modes:
command Mode (similar to MPU interface)
video mode (similar to RGB interface)-must transmit data in high-speed mode, supporting data transfer in 3 formats
? Non-burst Synchronous Pulse mode
? Non-burst Synchronous Event mode
? Burst Mode
• Transfer mode:
• High-speed signal modes (high-speed signaling mode)
• Low-Power signal mode (Low-power signaling mode)-use only data lane 0 (clock is from DP,DN).
• Frame Type
• Short Frame: 4 bytes (fixed)
• Long frame: 6~65541 bytes (variable)
• Two data lane high-speed transmission example

2. Short frame structure
• Frame Head (4 bytes)
• Data Identification (DI) 1 bytes
• Frame Data-2 bytes (fixed to 2 bytes in length)
• Error Detection (ECC) 1 bytes
• Frame Size
• Fixed length of 4 bytes
3. Long frame structure
• Frame Head (4 bytes)
• Data Identification (DI) 1 bytes
• Data Count-2 bytes (number of data fills)
• Error Detection (ECC) 1 bytes
• Data padding (0~65535 bytes)
• Length =wc* bytes
• End of frame: checksum (2 bytes)
• Frame Size:
• 4 + (0~65535) + 2 = 6 ~ 65541 bytes
4. Frame data type

Five, MIPI DSI signal Measurement Example
1. MIPI dsi signal measurement diagram in low power mode
2. Mipi's d-phy and DSI transmission modes and operating modes
Transmission modes for d-phy and DSi
•Low power (Low-power) signal mode (for control): 10MHz (max)
• High-speed (high-speed) signal mode (for high-speed data transfer): 80Mbps ~ 1gbps/lane
d-phy Mode of operation
Escape mode, high-speed (Burst) mode, Control mode
dsi Mode of operation
command Mode (similar to MPU interface)
video mode (similar to RGB interface)-data must be transferred in high-speed mode
3. Small conclusions
• Transfer mode and operating mode are different concepts
Video mode operation mode must use high-speed
Command mode operation mode does not specify a transmission mode using high-speed or low power, or
• Even if the external LCD module is video Mode, it is usuallyThe command mode is used to read and write registers when the LCD module is initialized because the data is not error prone and easy to measure at low speeds。
video mode can also use high-speed to send instructions, command mode can also be used high-speed, but there is no need to do so.

MIPI Agreement Chinese detailed