MiS603 Development Board the fourth chapter Flow lamp experiment

MiS603 Development Team

Date: 20150911

Company: Nanjing mi Lian Electronic Technology Co., Ltd.

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MiS603 Development Board the fourth chapter Flow lamp experiment

There are so many examples of running lights on the internet. In fact, as long as the master of the above crossover counting skills, the design of running lights is a very simple thing. From the 1.1.8 can be seen, led in the frequency of 1 times per second flashing, as long as the single LED light, to maintain the 1s highlight state, shift once per second, you can get a plurality of LED lights in line form flashing.

4.1 Hardware Analysis

LED lights in turn to the highlight of the 1s to maintain the shift display, a single LED light can be mapped to multiple LED lights. The overall block diagram of the design is shown below. As can be seen from the Mis603 schematic diagram, the FPGA IO at high level, led off, low power, led lit. Therefore, the setting of the LED initialization state is high, that is, off state.

4.2 Timing Design

? Input clock 50MHZ, to ensure that the LED light can be stabilized for 1 seconds. Defines the counter as 50000000/1=50000000. A 26-bit wide div_cnt counter is defined here. When the input clock rising edge is detected, div_cnt==26 ' d49_999999, the LED register is shifted to the right once and the counter is zeroed. 8 LED initialization status is 8 ' h01. When Led_o_r==8 ' h00, reset led_o_r==8 ' H01. Since the Mis603 is the FPGA's IO keep low, LED light is lit, so after the program, the LED storage register to reverse. In this way, 8 LED lights are cycled in turn.

4.3 Program source code

' Timescale 1ns/1ps

//-----------------------------------------------------------------------------------------------------

/*

* File name: water_lights

* Program Description:

Author

* Date Modified:

* Version number:

* All rights reserved: Nanjing mi Lian Electronic Technology Co., Ltd.

*/

//-----------------------------------------------------------------------------------------------------

Module Water_lights (

Input clk_i,

Input Rst_n_i,

Output [7:0] Led_o

);

Parameter hold_1s=26 ' d49_999999; For project

Parameter hold_1s=26 ' D49; For simulation

reg [25:0] div_cnt;

reg [7:0] led_o_r;

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

div_cnt<=0;

else if (div_cnt==hold_1s)

div_cnt<=0;

Else

Div_cnt<=div_cnt+1 ' B1;

End

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

Led_o_r<=8 ' h01;

else if (div_cnt==hold_1s)

led_o_r<=led_o_r<<1;

else if (led_o_r==8 ' h00)

Led_o_r<=8 ' h01;

Else

led_o_r<=led_o_r;

End

Assign Led_o=~led_o_r;

Endmodule

4.4 Pre-integrated wiring simulation timing

In the source program, set the Hold_1s parameter, to reduce the simulation wait time, analog LED lights lit environment. The parameters of the simulation are defined separately, and after the simulation is complete, you only need to modify this parameter. Its simulation results. It can be seen from led_o_r[0] to led_o_r[7] in this cycle to pull low.

4.5 Chipscope on-line Logic Analyzer simulation

Set up Logic Analyzer, take CLK_I_BUFGP as sampling clock, trigger signal is set to led_o_r[0]~led_o_r[7]. The fetch signal results as shown. As can be seen, the Led_o_r flip heel modelsim led_o output consistency.

4.6 Output Results

Program in the Hold_1s parameter changed to For_project option, recompile completed, the program downloaded to the board, you can see 8 of running lights, flashing merrily.

4.7 Summary

Running lights may be one of the necessary processes for each Development board. As you can see from the previous two sections, these are simple to implement as long as they understand the principle of frequency division counting. Changing different patterns, using FPGA to design a variety of counters, do some basic experiments, is conducive to the initial mastery of Verilog grammar and design logic.

MiS603 Development Board the fourth chapter Flow lamp experiment