MMU (Memory Management Unit) Features

MMU is short for Memory Management Unit. The Chinese name is the memory management unit. It is the control line used by the central processor (CPU) to manage Virtual Memory and physical memory, it is also responsible for ing virtual addresses to physical addresses and providing hardware-based Memory Access authorization.

I. History of MMU

Many years ago, when people were still using DOS or older operating systems, the computer's memory was still very small and generally calculated in K units, at that time, the program was not large, so although the memory capacity was small, it could still accommodate the program at that time. However, with the rise of the graphic interface and the increasing demand of users, the scale of applications also expands, and finally a problem arises in front of programmers, that is, the application is so large that the memory cannot accommodate the program. The common solution is to split the program into many fragments called overlay. Overwrite Block 0 is run first. At the end, it calls another overwrite block. Although the swap of the covered block is completed by the OS, it is time-consuming and labor-consuming and tedious to split the program first by the programmer. People must find a better way to fundamentally solve this problem. Soon, people found a way to use virtual memory ). the basic idea of the virtual memory is that the total size of the program, data, and stack can exceed the size of the physical memory. The operating system keeps the currently used part in the memory, the other unused parts are stored on the disk. For example, for a 16 MB program and a machine with a memory of only 4 MB, the operating system can choose which 4 MB of content is stored in the memory at each time, swap program segments between memory and disk as needed, so that the 16 M program can be run on a machine with only 4 M memory. This 16 M program does not need to be separated by programmers before running.

Ii. MMU-related concepts-address range, virtual address ing as physical address, and paging Mechanism

At any time, there is a set of addresses that can be generated by a program on the computer, which is called the address range. The size of this range is determined by the number of cpus. For example, a 32-bit CPU has a range of 0 ~ 0 xffffffff (4G), and for a 64-bit CPU, its address range is 0 ~ 0 xffffffffffffffff (64 t). This range is the address range that our program can produce. We call this address range a virtual address space, and a specific address in this space is called a virtual address. The physical address space and physical address correspond to the virtual address space and virtual address. In most cases, the physical address space of our system is only a subset of the virtual address space. Here is a simple example to illustrate the two. For a 32-bit x86 host with MB memory, its virtual address space ranges from 0 ~ 0 xffffffff (4G), and the physical address range is 0x000000000 ~ 0x0fffffff (256 m ).

On a machine that does not use virtual memory, the virtual address is directly sent to the memory bus, so that physical memory with the same address is read and written. When the virtual memory is used, the virtual address is not directly sent to the memory address bus, but to the memory management unit MMU to map the virtual address to the physical address.

Most systems that use virtual memory use a paging mechanism. The virtual address space is divided into units called pages, and the corresponding physical address space is also divided, in the unit of page frames ). the size of the page and page must be the same. In this example, we have a machine that can generate a 32-bit address. Its virtual address range is from 0 ~ 0 xffffffff (4G), and this machine only has a physical address of M, so it can run 4G programs, but this program cannot be transferred to the memory at a time to run. This machine must have an external memory (such as a disk or flash) that can store 4G programs to ensure that program fragments can be called as needed. In this example, the page size is 4 K, and the page size is the same as the page size-this must be ensured, because the transmission between memory and peripheral memory is always in the unit of page. Corresponding to 4G virtual address and M physical memory, they contain 1 m pages and 64 K pages respectively.

Iii. MMU Functions

1. Map a virtual address to a physical address

A modern multi-user multi-process operating system requires MMU to achieve the goal that each user process has its own address space. Using MMU, the operating system divides an address area. In this address area, the content of each process is not necessarily the same. For example, in Microsoft Windows, the address range of 4-2 GB is divided into user address space, and process a maps the executable file in address 0x400000 (4 m, process B maps the executable file in the address 0x400000 (4 m). If the read address of process a is 0x400000, when process B reads the address 0x400000, it reads the content mapped to ram by the executable file of.

This is the role of MMU in address translation.

2. provide hardware-based Memory Access Authorization

For many years, the microprocessor has been equipped with an on-chip memory management unit (MMU), which enables a single software thread to work in hardware to protect the address space. However, in many commercial real-time operating systems, MMU is not used even if the system contains the hardware.

When all threads of an application share the same memory space, any thread will intentionally or unintentionally destroy the code, data, or stack of other threads. Abnormal threads may even damage the kernel code or internal data structure. For example, a pointer error in a thread can easily cause the entire system to crash, or at least cause system operation exceptions.

In terms of security and reliability, process-based Real-time Operating Systems (RTOs) provide superior performance. To generate a process with a separate address space, RTOS only needs to generate some Ram-based data structures and enable MMU to enhance the protection of these data structures. The basic idea is to "access" a group of new logical addresses in each association conversion. MMU uses the current ing to map the logical addresses used during instruction calling or data read/write to the physical address of the memory. MMU also marks access to illegal logical addresses, which are not mapped to any physical addresses.

Although these processes increase the system overhead of accessing the memory using the query table, their implementation is very effective. At the process boundary, negligence or error operations will not occur, and defects in the user interface thread will not cause the code or data of other more critical threads to be damaged. Currently, in a complex embedded system with high reliability and security requirements, there are still operating systems without memory protection, which is incredible.

MMU can also be used to selectively map or demap pages to logical address spaces. The physical memory page maps to the logical space to keep the code of the current process. Other pages are used for data ing. Similarly, the physical memory page can maintain the thread stack of the process by ing. After each thread stack is unmapped, RTOS can easily retain the page content corresponding to the logical address. In this way, if the stack allocated by any thread overflows, the hardware memory Protection Failure will occur, and the kernel will suspend the thread without causing it to break other important memory areas in the address space, for example, another thread stack. This not only adds memory protection between threads but also between the same address space.

Memory protection (including such Stack Overflow detection) is usually very effective in application development. With memory protection, program errors will generate exceptions and can be immediately detected. It is tracked by the source code. If there is no memory protection, program errors will cause some minor faults that are difficult to trace. In fact, in a flat memory model, Ram is usually located on the zero page of the physical address, so even the release of NULL pointer reference cannot be detected.

Iv. MMU and CPU

1. x86 MMU Series

MMU is integrated into Intel's 80 Gbit/s CPU or updated CPU to provide 32bit 4 GB address space.

X86 MMU provides a 4 K/2 m/4 m page mode (based on different CPUs, different capabilities ), this section describes the 4 K paging mechanism used by most operating systems, and does not provide access check.

Involved registers

A) gdt

B) LDT

C) Cr0

D) 303.

E) segment register

Procedure for converting a virtual address to a physical address

A) segment register is used as the index of gdt or LDT to retrieve the corresponding gdt/LDT entry.

Note: Segment cannot be canceled, even in flat mode. it is wrong to disable segment register in flat mode. any Ram addressing command has the default segment assumption. the default segment is used unless the segment override prefix is used to change the segment of the current addressing instruction.

Entry format

Typedef struct

{

Uint16 limit_0_15;

Uint16 base_0_15;

Uint8 base_16_23;

Uint8 accessed: 1;

Uint8 readable: 1;

Uint8 conforming: 1;

Uint8 code_data: 1;

Uint8 app_system: 1;

Uint8 DPL: 2;

Uint8 present: 1;

Uint8 limit_16_19: 4;

Uint8 unused: 1;

Uint8 always_0: 1;

Uint8 seg_16_32: 1;

Uint8 granularity: 1;

Uint8 base_24_31;

} Code_seg_descriptor, * pcode_seg_descriptor;

Typedef struct

{

Uint16 limit_0_15;

Uint16 base_0_15;

Uint8 base_16_23;

Uint8 accessed: 1;

Uint8 writeable: 1;

Uint8 expanddown: 1;

Uint8 code_data: 1;

Uint8 app_system: 1;

Uint8 DPL: 2;

Uint8 present: 1;

Uint8 limit_16_19: 4;

Uint8 unused: 1;

Uint8 always_0: 1;

Uint8 seg_16_32: 1;

Uint8 granularity: 1;

Uint8 base_24_31;

} Data_seg_descriptor, * pdata_seg_descriptor;

There are four entry formats. Here, the entry formats of code segment and data segment are provided. in flat mode, the entry is 0 at base_0_15, base_16_23, and 0xfffff at limit_0_15 and limit_16_19. granularity is 1. the table name segment address space is a 4G address space from 0 to 0xffffffff.

B) obtain the base address and limit from the segment. The address to be accessed is checked first to see if it exceeds the segment limit.

C) The address + base address to be accessed to form a virtual address that requires 32-bit access. The address is interpreted as follows:

Typedef struct

{

Uint32 offset: 12;

Uint32 page_index: 10;

Uint32 pdbr_index: 10;

} Va, * lpva;

D) pdbr_index is used as the index of F3. a data structure defined below is obtained.

Typedef struct

{

Uint8 present: 1;

Uint8 writable: 1;

Uint8 Supervisor: 1;

Uint8 writethrough: 1;

Uint8 cachedisable: 1;

Uint8 accessed: 1;

Uint8 reserved1: 1;

Uint8 pagesize: 1;

Uint8 ignoreed: 1;

Uint8 AVL: 3;

Uint8 ptadr_12_15: 4;

Uint16 ptadr_16_31;

} PVDF, * lppdde;

E) retrieve the address of the page table from the table and use page_index as the index to obtain the following data structure:

Typedef struct

{

Uint8 present: 1;

Uint8 writable: 1;

Uint8 Supervisor: 1;

Uint8 writethrough: 1;

Uint8 cachedisable: 1;

Uint8 accessed: 1;

Uint8 dirty: 1;

Uint8 PTA: 1;

Uint8 Global: 1;

Uint8 AVL: 3;

Uint8 ptadr_12_15: 4;

Uint16 ptadr_16_31;

} PTE, * lppte;

F) Obtain base address of the real physical address of the page from the Pte. The base address table name is physical address. The height is 20 bits. the offset of the virtual address is the physical address.

2. MMU of ARM Series

The CPU produced by arm and MMU exist as a coprocessor. Different series have different combinations. You need to query datasheet to check whether MMU exists. If yes, it must be a coprocessor numbered 15. A 32-bit 4G address space is provided.

The paging mechanism provided by arm MMU is 1 K/4 K/64 K. This article describes the 4 K mode that is commonly used by operating systems.

The involved registers are all in the coprocessor 15.

Arm does not have a segment register and is a real flat-mode CPU. Given an address, this address can be understood as the following data structure:

Typedef struct

{

Uint32 offset: 12;

Uint32 page_index: 8;

Uint32 pdbr_index: 12;

} Va, * lpva;

Get the BIT14-31 from MMU register 2, pdbr_index is the index of this table, each entry is 4 byte size, structure is

Typedef struct

{

Uint32 type: 2; // always set to 01b

Uint32 writebackcacheable: 1;

Uint32 writethroughcacheable: 1;

Uint32 ignore: 1; // set to 1B always

Uint32 domain: 4;

Uint32 Reserved: 1; // set 0

Uint32 base_addr: 22;

} PVDF, * lppdde;

Obtain the following structure of the array, and use page_index as the index to retrieve the content.

Typedef struct

{

Uint32 type: 2; // always set to 11b

Uint32 ignore: 3; // set to 100b always

Uint32 domain: 4;

Uint32 Reserved: 3; // set 0

Uint32 base_addr: 20;

} PTE, * lppte;

The base address obtained from the PTE and the upper offset constitute the physical address.

Other bits in the PVDF/PTE are used for access control. What we will talk about here is that everything is normal and physical addresses are normally combined.

Differences in ARM/x86 MMU usage

1. x86 always has the segment concept, while arm does not (there is no segment register .).

2. arm has a domain concept. It is used for Access authorization. This is a concept not available in x86. When a general-purpose OS tries to apply to the CPU of both, domain usage is generally discarded.